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93LCS66-IP 데이터시트 PDF




Microchip Technology에서 제조한 전자 부품 93LCS66-IP은 전자 산업 및 응용 분야에서
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부품번호 93LCS66-IP 기능
기능 2K/4K 2.5V Microwire Serial EEPROM with Software Write Protect
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93LCS66-IP 데이터시트, 핀배열, 회로
93LC66A/B
4K 2.5V Microwire® Serial EEPROM
FEATURES
• Single supply with operation down to 2.5V
• Low power CMOS technology
- 1 mA active current (typical)
- 1 µA standby current (maximum)
• 512 x 8 bit organization (93LC66A)
• 256 x 16 bit organization (93LC66B)
• Self-timed ERASE and WRITE cycles
(including auto-erase)
• Automatic ERAL before WRAL
• Power on/off data protection circuitry
• Industry standard 3-wire serial interface
• Device status signal during ERASE/WRITE cycles
• Sequential READ function
• 1,000,000 E/W cycles guaranteed
• Data retention > 200 years
• 8-pin PDIP/SOIC and 8-pin TSSOP packages
• Available for the following temperature ranges:
- Commercial (C):
- Industrial (I):
0°C to +70°C
-40°C to +85°C
PACKAGE TYPE
DIP
SOIC
BLOCK DIAGRAM
MEMORY
ARRAY
ADDRESS
DECODER
DI
CS
CLK
DATA
REGISTER
ADDRESS
COUNTER
OUTPUT
BUFFER
DO
MODE
DECODE
LOGIC
CLOCK
GENERATOR
Vcc
Vss
DESCRIPTION
The Microchip Technology Inc. 93LC66A/B are 4K-bit,
low voltage serial Electrically Erasable PROMs. The
device memory is configured as x8 (93LC66A) or
x16 bits (93LC66B). Advanced CMOS technology
makes these devices ideal for low power nonvolatile
memory applications. The 93LC66A/B is available in
standard 8-pin DIP, surface mount SOIC, and TSSOP
packages. The 93LC66AX/BX are only offered in a
150-mil SOIC package.
SOIC
TSSOP
CS 1
CLK 2
DI 3
DO 4
8 Vcc
CS
7 NC
CLK
6 NC
DI
5 Vss
DO
1
2
3
4
8 VCC
NC 1
7 NC
Vcc 2
6 NC
CS 3
5 Vss CLK 4
CS 1
8 NC CLK 2
DI 3
7 Vss
DO 4
6 DO
5 DI
8 Vcc
7 NC
6 NC
5 Vss
Microwire is a registered trademark of Motorola.
1998 Microchip Technology Inc.
DS21209C-page 1




93LCS66-IP pdf, 반도체, 판매, 대치품
93LC66A/B
3.0 FUNCTIONAL DESCRIPTION
Instructions, addresses, and write data are clocked into
the DI pin on the rising edge of the clock (CLK). The DO
pin is normally held in a HIGH-Z state except when
reading data from the device, or when checking the
READY/BUSY status during a programming operation.
The READY/BUSY status can be verified during an
ERASE/WRITE operation by polling the DO pin; DO
low indicates that programming is still in progress, while
DO high indicates the device is ready. The DO will enter
the HIGH-Z state on the falling edge of the CS.
3.1 START Condition
The START bit is detected by the device if CS and DI
are both high with respect to the positive edge of CLK
for the first time.
Before a START condition is detected, CS, CLK, and DI
may change in any combination (except to that of a
START condition), without resulting in any device oper-
ation (ERASE, ERAL, EWDS, EWEN, READ, WRITE,
and WRAL). As soon as CS is high, the device is no
longer in the standby mode.
An instruction following a START condition will only be
executed if the required amount of opcodes,
addresses, and data bits for any particular instruction is
clocked in.
After execution of an instruction (i.e., clock in or out of
the last required address or data bit) CLK and DI
become dont care bits until a new START condition is
detected.
FIGURE 3-1: SYNCHRONOUS DATA TIMING
CS VIH
VIL
TCSS
TCKH
VIH
CLK
VIL
VIH
DI
VIL
TDIS
DO VOH
(READ) VOL
DO VOH
(PROGRAM) VOL
TSV
TDIH
TPD
Note: AC Test Conditions: VIL = 0.4V, VIH = 2.4V.
3.2 Data In (DI) Data Out (DO)
It is possible to connect the Data In (DI)and Data Out
(DO)pins together. However, with this configuration, if
A0 is a logic-high level, it is possible for a bus conflict
to occur during the dummy zerothat precedes the
READ operation. Under such a condition the voltage
level seen at Data Out is undefined and will depend
upon the relative impedances of Data Out and the sig-
nal source driving A0. The higher the current sourcing
capability of A0, the higher the voltage at the Data Out
pin.
3.3 Data Protection
During power-up, all programming modes of operation
are inhibited until VCC has reached a level greater than
2.2V. During power-down, the source data protection
circuitry acts to inhibit all programming modes when
Vcc has fallen below 2.2V at nominal conditions.
The ERASE/WRITE Disable (EWDS) and ERASE/
WRITE Enable (EWEN) commands give additional pro-
tection against accidentally programming during nor-
mal operation.
After power-up, the device is automatically in the
EWDS mode. Therefore, an EWEN instruction must be
performed before any ERASE or WRITE instruction
can be executed.
TCKL
TCSH
TPD
STATUS VALID
TCZ
TCZ
DS21209C-page 4
1998 Microchip Technology Inc.

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93LCS66-IP 전자부품, 판매, 대치품
93LC66A/B
3.8 WRITE
The WRITE instruction is followed by 8 bits (93LC66A)
or 16 bits (93LC66B) of data which are written into the
specified address. After the last data bit is put on the DI
pin, the falling edge of CS initiates the self-timed auto-
erase and programming cycle.
The DO pin indicates the READY/BUSY status of the
device, if CS is brought high after a minimum of 250 ns
low (TCSL) and before the entire write cycle is complete.
DO at logical 0indicates that programming is still in
progress. DO at logical 1indicates that the register at
the specified address has been written with the data
specified and the device is ready for another instruc-
tion.
FIGURE 3-7: WRITE TIMING
CS
3.9 Write All (WRAL)
The Write All (WRAL) instruction will write the entire
memory array with the data specified in the command.
The WRAL cycle is completely self-timed and com-
mences at the falling edge of the CS. Clocking of the
CLK pin is not necessary after the device has entered
the WRAL cycle. The WRAL command does include an
automatic ERAL cycle for the device. Therefore, the
WRAL instruction does not require an ERAL instruc-
tion, but the chip must be in the EWEN status.
The DO pin indicates the READY/BUSY status of the
device if CS is brought high after a minimum of 250 ns
low (TCSL).
TCSL
CLK
DI 1 0 1 An ••• A0 Dx ••• D0
HIGH-Z
DO
FIGURE 3-8: WRAL TIMING
CS
CLK
TSV
BUSY
Twc
READY
TCZ
HIGH-Z
TCSL
DI 1 0 0 0 1 X ••• X Dx ••• D0
HIGH-Z
DO
Guaranteed at Vcc = 4.5V to +6.0V.
TSV TCZ
BUSY
TWL
READY
HIGH-Z
1998 Microchip Technology Inc.
DS21209C-page 7

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