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95SQ015 데이터시트, 핀배열, 회로
93LCS56/66
2K/4K 2.5V Microwire® Serial EEPROM with Software Write Protect
FEATURES
• Single supply with programming operation down
to 2.5V
• Low power CMOS technology
- 1 mA active current typical
- 5 µA standby current (typical) at 3.0V
• x16 memory organization
- 128x16 (93LCS56)
- 256x16 (93LCS66)
• Software write protection of user defined memory
space
• Self timed erase and write cycles
• Automatic ERAL before WRAL
• Power on/off data protection
• Industry standard 3-wire serial I/O
• Device status signal during E/W
• Sequential READ function
• 1,000,000 E/W cycles guaranteed
• Data retention > 200 years
• 8-pin PDIP/SOIC and 14-pin SOIC packages
• Temperature ranges supported
- Commercial (C):
- Industrial (I):
0˚C to +70˚C
-40˚C to +85˚C
BLOCK DIAGRAM
VCC
V SS
MEMORY
ARRAY
ADDRESS
DECODER
DI
PRE
PE
CS
DATA REGISTER
MODE
DECODE
LOGIC
ADDRESS
COUNTER
OUTPUT
BUFFER
DO
CLOCK
CLK GENERATOR
DESCRIPTION
The Microchip Technology Inc. 93LCS56/66 are low volt-
age Serial Electrically Erasable PROMs with memory
capacities of 2K bits/4K bits respectively. A write protect
register is included in order to provide a user defined
region of write protected memory. All memory locations
greater than or equal to the address placed in the write
protect register will be protected from any attempted write
or erase operation. It is also possible to protect the
address in the write protect register permanently by using
a one time only instruction (PRDS). Any attempt to alter
data in a register whose address is equal to or greater
than the address stored in the protect register will be
aborted. Advanced CMOS technology makes this device
ideal for low power non-volatile memory applications.
PACKAGE TYPES
CS
CLK
DI
DO
DIP
18
27
36
45
93LCS56
93LCS66
VCC
PRE
PE
VSS
CS
CLK
DI
DO
SOIC
18
27
36
45
93LCS56
93LCS66
VCC
PRE
PE
VSS
SOIC
NC 1
CS 2
CLK 3
NC 4
DI 5
DO 6
NC 7
14 NC
13 VCC
12 PRE
11 NC
10 PE
9 VSS
8 NC
93LCS56
93LCS66
Microwire is a registered trademark of National Semiconductor Incorporated.
© 1996 Microchip Technology Inc.
Preliminary
DS11181D-page 1
This document was created with FrameMaker 4 0 4




95SQ015 pdf, 반도체, 판매, 대치품
93LCS56/66
2.0 FUNCTIONAL DESCRIPTION
The 93LCS56/66 is organized as 128/256 registers by
16 bits. Instructions, addresses and write data are
clocked into the DI pin on the rising edge of the clock
(CLK). The DO pin is normally held in a high-Z state
except when reading data from the device, or when
checking the ready/busy status during a programming
operation. The ready/busy status can be verified during
an Erase/Write operation by polling the DO pin; DO low
indicates that programming is still in progress, while DO
high indicates the device is ready. The DO will enter the
high-Z state on the falling edge of the CS.
2.1 START Condition
The START bit is detected by the device if CS and DI
are both HIGH with respect to the positive edge of CLK
for the first time.
Before a START condition is detected, CS, CLK, and DI
may change in any combination (except to that of a
START condition), without resulting in any device oper-
ation (READ, WRITE, ERASE, EWEN, EWDS, ERAL,
WRAL, PRREAD, PREN, PRCLEAR, PRWRITE, and
PRDS). As soon as CS is HIGH, the device is no longer
in the standby mode.
An instruction following a START condition will only be
executed if the required amount of opcode, address
and data bits for any particular instruction is clocked in.
After execution of an instruction (i.e., clock in or out of
the last required address or data bit) CLK and DI
become don't care bits until a new start condition is
detected.
2.2 DI/DO
It is possible to connect the Data In and Data Out pins
together. However, with this configuration it is possible
for a “bus conflict” to occur during the “dummy zero” that
precedes the READ operation, if A0 is a logic HIGH
level. Under such a condition the voltage level seen at
Data Out is undefined and will depend upon the relative
impedances of Data Out and the signal source driving
A0. The higher the current sourcing capability of A0, the
higher the voltage at the Data Out pin.
2.3 Data Protection
During power-up, all programming modes of operation
are inhibited until VCC has reached a level greater than
1.4V. During power-down, the source data protection
circuitry acts to inhibit all programming modes when
VCC has fallen below 1.4V.
The EWEN and EWDS commands give additional pro-
tection against accidentally programming during nor-
mal operation.
After power-up, the device is automatically in the
EWDS mode. Therefore, an EWEN instruction must be
performed before any ERASE or WRITE instruction can
be executed.
2.4 READ
The READ instruction outputs the serial data of the
addressed memory location on the DO pin. A dummy
zero bit precedes the 16 bit output string. The output
data bits will toggle on the rising edge of the CLK and
are stable after the specified time delay (TPD). Sequen-
tial read is possible when CS is held high. The memory
data will automatically cycle to the next register and
output sequentially.
2.5 Erase/Write Enable and Disable
(EWEN, EWDS)
The 93LCS56/66 powers up in the Erase/Write Disable
(EWDS) state. All programming modes must be pre-
ceded by an Erase/Write Enable (EWEN) instruction.
The PE pin MUST be held “high” while loading the
EWEN instruction. Once the EWEN instruction is exe-
cuted, programming remains enabled until an EWDS
instruction is executed or VCC is removed from the
device. To protect against accidental data disturb, the
EWDS instruction can be used to disable all Erase/
Write functions and should follow all programming
operations. Execution of a READ instruction is indepen-
dent of both the EWEN and EWDS instructions.
2.6 ERASE
The ERASE instruction forces all data bits of the spec-
ified address to the logical “1” state. CS is brought low
following the loading of the last address bit. This falling
edge of the CS pin initiates the self-timed programming
cycle. The PE pin MUST be latched “high” during load-
ing the ERASE instruction but becomes a “don't care”
after loading the instruction.
The DO pin indicates the READY/BUSY status of the
device if CS is brought high after a minimum of 250 ns
low (TCLS). DO at logical “0” indicates that program-
ming is still in progress. DO at logical “1” indicates that
the register at the specified address has been erased
and the device is ready for another instruction. ERASE
instruction is valid if specified address is unprotected.
The ERASE cycle takes 4 ms per word typical.
2.7 WRITE
The WRITE instruction is followed by 16 bits of data
which are written into the specified address. After the
last data bit is put on the DI pin, CS must be brought low
before the next rising edge of the CLK clock. Both CS
and CLK must be low to initiate the self-timed auto-
erase and programming cycle. The PE pin MUST be
latched “high” while loading the WRITE instruction but
becomes a “don't care” thereafter.
DS11181D-page 4
Preliminary
© 1996 Microchip Technology Inc.

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95SQ015 전자부품, 판매, 대치품
FIGURE 2-4: EWDS TIMING
CS
CLK
93LCS56/66
TCSL
DI
1 00 00 X
•••
X
FIGURE 2-5: WRITE TIMING
PE
6 DON'T CARE BITS
CS TCSL
PRE = 0
PE = X
DO = TRI-STATE
CLK
DI 1 0 1 A7 • • • A0 D15 • • • D0
TRI-STATE
DO
• Address bit A7 becomes a "don't care" for 93LCS56.
FIGURE 2-6: WRAL TIMING
PRE = 0
PE
CS
BUSY
TWC
TCSL
READY
CLK
DI 1 0 0 0 1 X • • • X D15 • • • D0
DO TRI-STATE
Guaranteed at VCC = 4.5V to 6.0V
Protect Register must be cleared PRE = 0
6 DON'T CARE BITS
BUSY READY TRISTATE
TWL
© 1996 Microchip Technology Inc.
Preliminary
DS11181D-page 7

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