PDF 9639 Data sheet ( Hoja de datos )

Número de pieza	9639
Descripción	N-CHANNEL 150V - 0.045 OHM - 5A SO-8 LOW GATE CHARGE STripFET POWER MOSFET
Fabricantes	STMicroelectronics
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No Preview Available ! ST95P04 SERIAL ACCESS SPI BUS 4K (512 x 8) EEPROM 1 MILLION ERASE/WRITE CYCLES 40 YEARS DATA RETENTION SINGLE 3V to 5.5V SUPPLY VOLTAGE SPI BUS COMPATIBLE SERIAL INTERFACE 1 MHz CLOCK RATE MAX BLOCK WRITE PROTECTION STATUS REGISTER 16 BYTE PAGE MODE WRITE PROTECT SELF-TIMED PROGRAMMING CYCLE E.S.D.PROTECTION GREATER than 4000V The ST95P04 will be replaced shortly by the updated version ST95040 NOT FOR NEW DESIGN 8 1 PSDIP8 (B) 0.25mm Frame 8 1 SO8 (M) DESCRIPTION The ST95P04 is a 4K bit Electrically Erasable Programmable Memory (EEPROM) fabricated with SGS-THOMSON’s High Endurance Single Polysili- con CMOS technology. The 4K bit memory is or- ganised as 32 pages of 16 bytes. The memory is accessed by a simple SPI bus compatible serial interface. The bus signals are a serial clock input (C), a serial data input (D) and a serial data output (Q). The device connected to the bus is selected when the chip select input (S) goes low. Commu- nications with the chip can be interrupted with a hold input (HOLD). The write operation is disabled by a write protect input (W). Table 1. Signal Names C D Q S W HOLD VCC VSS Serial Clock Serial Data Input Serial Data Output Chip Select Write Protect Hold Supply Voltage Ground Figure 1. Logic Diagram VCC D C S W HOLD ST95P04 VSS Q AI01063B June 1996 1/16 1 page ST95P04 Table 5. AC Characteristics (TA = 0 to 70°C or –40 to 85°C; VCC = 3V to 5.5V) Symbol Alt Parameter Test Condition Min Max Unit fC fC Clock Frequency D.C. 1 MHz tSLCH tSU S Setup Time 100 ns tCLSH tSH S Hold Time 100 ns tCH tWH Clock High Time 400 ns tCL tWL Clock Low Time 400 ns tCLCH tRC Clock Rise Time 1 µs tCHCL tFC Clock Fall Time 1 µs tDVCH tDSU Data In Setup Time 100 ns tCHDX tDH Data In Hold Time 100 ns tDLDH tRI Data In Rise Time 1 µs tDHDL tFI Data In Fall Time 1 µs tHXCH tHSU HOLD Setup Time 100 ns tCLHX tHH HOLD Hold Time 100 ns tSHSL tCS S Deselect Time 400 ns tSHQZ tDIS Output Disable Time 300 ns tQVCL tV Clock Low to Output Valid 400 ns tCLQX tHO Output Hold Time 0 ns tQLQH tRO Output Rise Time 150 ns tQHQL tFO Output Fall Time 150 ns tHHQX tLZ HOLD High to Output Low-Z 300 ns tHLQZ tHZ HOLD Low to Output High-Z 300 ns tW (1) tW Write Cycle Time 10 ms Note: 1. Not enough characterisation data were available on this parameter at the time of issue this Data Sheet. The typical value is well below 5ms, the maximum value will be reviewed and lowered when sufficient data is available. 5/16 5 Page Figure 11. Page Write Operation Sequence ST95P04 S 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 C INSTRUCTION BYTE ADDRESS DATA BYTE 1 DA 765432107 S 24 25 26 27 28 29 30 31 C DATA BYTE 2 DATA BYTE N DATA BYTE 16 D 765432107654321076543210 AI01069 Figure 12. RDSR: Read Status Register Sequence S 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 C INSTRUCTION D STATUS REG. OUT HIGH IMPEDANCE Q 76543210 MSB AI01433 11/16 11 Page

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9639	N-CHANNEL 150V - 0.045 OHM - 5A SO-8 LOW GATE CHARGE STripFET POWER MOSFET	STMicroelectronics

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