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A29L400TM-90 데이터시트 PDF




AMIC Technology에서 제조한 전자 부품 A29L400TM-90은 전자 산업 및 응용 분야에서
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부품번호 A29L400TM-90 기능
기능 512K X 8 Bit / 256K X 16 Bit CMOS 3.0 Volt-only/ Boot Sector Flash Memory
제조업체 AMIC Technology
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A29L400TM-90 데이터시트, 핀배열, 회로
A29L400 Series
Preliminary
512K X 8 Bit / 256K X 16 Bit CMOS 3.0 Volt-only,
Boot Sector Flash Memory
Features
n Single power supply operation
- Full voltage range: 2.7 to 3.6 volt read and write
operations for battery-powered applications
- Regulated voltage range: 3.0 to 3.6 volt read and write
operations for compatibility with high performance 3.3
volt microprocessors
n Access times:
- 70/90 (max.)
n Current:
- 4 mA typical active read current
- 20 mA typical program/erase current
- 200 nA typical CMOS standby
- 200 nA Automatic Sleep Mode current
n Flexible sector architecture
- 16 Kbyte/ 8 KbyteX2/ 32 Kbyte/ 64 KbyteX7 sectors
- 8 Kword/ 4 KwordX2/ 16 Kword/ 32 KwordX7 sectors
- Any combination of sectors can be erased
- Supports full chip erase
- Sector protection:
A hardware method of protecting sectors to prevent
any inadvertent program or erase operations within
that sector. Temporary Sector Unprotect feature
allows code changes in previously locked sectors
n Extended operating temperature range: -45°C ~ +85°C
for –U series
n Unlock Bypass Program Command
- Reduces overall programming time when issuing
multiple program command sequence
n Top or bottom boot block configurations available
n Embedded Algorithms
- Embedded Erase algorithm will automatically erase
the entire chip or any combination of designated
sectors and verify the erased sectors
- Embedded Program algorithm automatically writes
and verifies data at specified addresses
n Typical 100,000 program/erase cycles per sector
n 20-year data retention at 125°C
- Reliable operation for the life of the system
n Compatible with JEDEC-standards
- Pinout and software compatible with single-power-
supply Flash memory standard
- Superior inadvertent write protection
n Data Polling and toggle bits
- Provides a software method of detecting completion
of program or erase operations
n Ready / BUSY pin (RY / BY )
- Provides a hardware method of detecting completion
of program or erase operations (not available on 44-
pin SOP)
n Erase Suspend/Erase Resume
- Suspends a sector erase operation to read data from,
or program data to, a non-erasing sector, then
resumes the erase operation
n Hardware reset pin (RESET )
- Hardware method to reset the device to reading array
data
n Package options
- 44-pin SOP or 48-pin TSOP (I) or 48-ball TFBGA
PRELIMINARY (October, 2002, Version 0.2)
1
AMIC Technology, Inc.




A29L400TM-90 pdf, 반도체, 판매, 대치품
Block Diagram
VCC
VSS
RY/BY
RESET
WE
BYTE
CE
OE
State
Control
Command
Register
A0-A17
VCC Detector
A29L400 Series
Sector Switches
Erase Voltage
Generator
I/O0 - I/O 15 (A-1)
Input/Output
Buffers
PGM Voltage
Generator
Chip Enable
Output Enable
Logic
STB Data Latch
Timer
STB Y-Decoder
X-decoder
Y-Gating
Cell Matrix
Pin Descriptions
Pin No.
A0 - A17
I/O0 - I/O14
I/O15 (A-1)
I/O15
A-1
CE
WE
OE
RESET
BYTE
RY/ BY
VSS
VCC
NC
Description
Address Inputs
Data Inputs/Outputs
Data Input/Output, Word Mode
LSB Address Input, Byte Mode
Chip Enable
Write Enable
Output Enable
Hardware Reset
Selects Byte Mode or Word Mode
Ready/ BUSY - Output
Ground
Power Supply
Pin not connected internally
PRELIMINARY (October, 2002, Version 0.2)
4
AMIC Technology, Inc.

4페이지










A29L400TM-90 전자부품, 판매, 대치품
A29L400 Series
Output Disable Mode
When the OE input is at VIH, output from the device is
disabled. The output pins are placed in the high impedance
state.
RESET : Hardware Reset Pin
The RESET pin provides a hardware method of resetting
the device to reading array data. When the system drives
the RESET pin low for at least a period of tRP, the device
immediately terminates any operation in progress, tristates
all data output pins, and ignores all read/write attempts for
the duration of the RESET pulse. The device also resets
the internal state machine to reading array data. The
operation that was interrupted should be reinitiated once
the device is ready to accept another command sequence,
to ensure data integrity.
Current is reduced for the duration of the RESET pulse.
When RESET is held at VSS ± 0.3V, the device draws
CMOS standby current (ICC4 ). If RESETis held at VIL but
not within VSS ± 0.3V, the standby current will be greater.
The RESET pin may be tied to the system reset circuitry. A
system reset would thus also reset the Flash memory,
enabling the system to read the boot-up firmware from the
Flash memory.
If RESET is asserted during a program or erase operation,
the RY/ BY pin remains a “0” (busy) until the internal reset
operation is complete, which requires a time tREADY (during
Embedded Algorithms). The system can thus monitor
RY/ BY to determine whether the reset operation is
complete. If RESET is asserted when a program or erase
operation is not executing (RY/ BY pin is “1”), the reset
operation is completed within a time of tREADY (not during
Embedded Algorithms). The system can read data tRH after
the RESET pin return to VIH.
Refer to the AC Characteristics tables for RESET
parameters and diagram.
PRELIMINARY (October, 2002, Version 0.2)
7
AMIC Technology, Inc.

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부품번호상세설명 및 기능제조사
A29L400TM-90

512K X 8 Bit / 256K X 16 Bit CMOS 3.0 Volt-only/ Boot Sector Flash Memory

AMIC Technology
AMIC Technology

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