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PDF CS49330 Data sheet ( Hoja de datos )
| Número de pieza | CS49330 | |
| Descripción | Multi-Standard Audio Decoder Family | |
| Fabricantes | Cirrus Logic | |
| Logotipo |  |
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CS49300 Family DSP
Multi-Standard Audio Decoder Family
Features
Description
z CS4930X: DVD Audio Sub-family
— PES Layer decode for A/V sync
— DVD Audio Pack Layer Support
— Meridian Lossless Packing Specification (MLP)™
— Dolby Digital™, Dolby Pro Logic II™
— MPEG-2, Advanced Audio Coding Algorithm (AAC)
— MPEG Multichannel
— DTS Digital Surround™, DTS-ES Extended Surround™
z CS4931X: Broadcast Sub-family
— PES Layer decode for A/V sync
— Dolby Digital
— MPEG-2, Advanced Audio Coding Algorithm (AAC)
— MPEG-1 (Layers 1, 2, 3) Stereo
— MPEG-2 (Layers 2, 3) Stereo
z CS4932X: AVR Sub-family
— Dolby Digital, Dolby Pro Logic II
— DTS & DTS-ES decoding with integrated DTS tables
— Cirrus Original Surround 5.1 PCM Enhancement
— MPEG-2, Advanced Audio Coding Algorithm (AAC)
— MPEG Multichannel
— MP3 (MPEG-1, Layer 3)
z CS49330: General Purpose Audio DSP
— THX® Surround EX™ and THX® Ultra2 Cinema
— General Purpose AVR and Broadcast Audio Decoder
(MPEG Multichannel, MPEG Stereo, MP3, C.O.S.)
— Car Audio
z Features are a super-set of the CS4923/4/5/6/7/8/9
— 8 channel output, including dual zone output capability
— Dynamic Channel Remapability
— Supports up to 192 kHz Fs @ 24-bit throughput
— Increased memory/MIPs
— SRAM Interface for increased delay and buffer capability
— Dual-Precision Bass Manager
— Enhance your system functionality via firmware
upgrades through the Crystal WareTM Software
Licensing Program
The CS493XX is a family of multichannel audio decoders
intended to supersede the CS4923/4/5/6/7/8/9 family as the
leader of audio decoding in both the DVD, broadcast and
receiver markets. The family will be split into parts tailored for
each of these distinct market segments.
For the DVD market, parts will be offered which support Meridian
Lossless Packing (MLP), Dolby Digital, Dolby Pro Logic II,
MPEG Multichannel, DTS Digital Surround, DTS-ES, AAC, and
subsets thereof. For the receiver market, parts will be offered
which support Dolby Digital, Dolby Pro Logic II, MPEG
Multichannel, DTS Digital Surround, DTS-ES, AAC, and various
virtualizers and PCM enhancement algorithms such as HDCD®,
DTS Neo:6TM, LOGIC7®, and SRS Circle Surround II®. For the
broadcast market, parts will be offered which support Dolby
Digital, AAC, MPEG-1, Layers 1,2 and 3, MPEG-2, Layers 2 and
3.
Under the Crystal brand, Cirrus Logic is the only single supplier
of high-performance 24-bit multi-standard audio DSP decoders,
DSP firmware, and high-resolution data converters. This
combination of DSPs, system firmware, and data converters
simplify rapid creation of world-class high-fidelity digital audio
products for the Internet age.
Ordering Information: See page 85
CS49300
CS49310
CS49311
CS49312
CS49325
CS49326
CS49329
CS49330
CS49330
CS49330
APPLICATION
DVD Audio
Broadcast
Broadcast
Broadcast
AVR
AVR
AVR
Car Audio DSP
General Purpose
Post-Processor
CORE DECODER FUNCTIONALITY
MLP, AC-3, AAC, DTS, MPEG 5.1, MP3, etc.
AAC, AC-3, MPEG Stereo, MP3, etc.
AAC, MPEG Stereo, MP3, etc.
AC-3, MPEG Stereo, MP3, etc.
AC-3, COS, MPEG 5.1, MP3, etc.
AC-3, DTS, COS, MPEG 5.1, MP3, etc.
AC-3, AAC, DTS, MPEG 5.1, MP3, etc.
Car Audio Code
MPEG 5.1, MPEG Stereo, MP3, C.O.S., etc
DPP, THX Surround EX, THX Ultra2 Cinema
RESET
RD, WR, SCDIO,
DATA7:0,
R/W, DS, SCDOUT,
EMAD7:0,
EMOE, EMWR, PSEL, A0, A1,
GPIO7:0 CS GPIO11 GPIO10 GPIO9 SCCLK SCDIN
ABOOT,
INTREQ
EXTMEM,
GPIO8
CMPDAT,
SDATAN2
CMPCLK,
SCLKN2
CMPREQ,
LRCLKN2
SCLKN1,
STCCLK2
LRCLKN1
SDATAN1
CLKIN
CLKSEL
Compressed
Data Input
Interface
Framer
Shifter
Digital
Audio
Input
Interface
Input
Buffer
Controller
RAM Input
Buffer
PLL
Clock Manager
Parallel or Serial Host Interface
24-Bit
DSP Processing
RAM RAM
Program Data
Memory Memory
ROM ROM
Program Data
Memory Memory
STC
RAM
Output
Buffer
DD
DC
Output
Formatter
MCLK
SCLK
LRCLK
AUDATA[2.0]
XMT958/AUDATA3
FILT2 FILT1 VA AGND
Preliminary Product Information
DGND[3:1] VD[3:1]
This document contains information for a new product.
Cirrus Logic reserves the right to modify this product without notice.
P.O. Box 17847, Austin, Texas 78760
(512) 445 7222 FAX: (512) 445 7581
http://www.cirrus.com
Copyright Cirrus Logic, Inc. 2002
(All Rights Reserved)
MAR ‘02
DS339PP4
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1 page  
CS49300 Family DSP
Figure 38. Fast Autoboot Sequence Using GFABT Codes ...............................................................60
Figure 39. Performing a Reset ..........................................................................................................62
Figure 40. Non-Paged Memory .........................................................................................................64
Figure 41. Example Contents of a Paged 32 Kilobytes External Memory (Total 256 Kilobytes) .......64
Figure 42. CDB49300-MEMA.0 Daughter Card for the CDB4923/30-REV-A.0 ................................66
Figure 43. I2S Format ........................................................................................................................68
Figure 44. Left Justified Format (Rising Edge Valid SCLK) ...............................................................68
Figure 45. Multichannel Format .........................................................................................................68
LIST OF TABLES
Table 1. PLL Filter Component Values .............................................................................................. 25
Table 2. Host Modes .......................................................................................................................... 32
Table 3. SPI Communication Signals................................................................................................. 33
Table 4. I2C® Communication Signals ............................................................................................. 35
Table 5. Parallel Input/Output Registers ............................................................................................ 42
Table 6. Intel Mode Communication Signals...................................................................................... 43
Table 7. Motorola Mode Communication Signals .............................................................................. 45
Table 8. Memory Interface Pins ......................................................................................................... 49
Table 9. Boot Write Messages ........................................................................................................... 52
Table 10. Boot Read Messages......................................................................................................... 52
Table 11. Reduced Autoboot Times using GFABT8.LD, GFABT6.LD, and GFABT4.LD
on a CS493264-CL Rev. G DSP........................................................................................................ 59
Table 12. Memory Requirements for Example 5.1, 6.1 and 7.1 Channel Systems ........................... 63
Table 13. Digital Audio Input Port ...................................................................................................... 68
Table 14. Compressed Data Input Port.............................................................................................. 69
Table 15. Digital Audio Output Port.................................................................................................... 70
Table 16. MCLK/SCLK Master Mode Ratios...................................................................................... 71
Table 17. Output Channel Mapping ................................................................................................... 71
Table 18. Input Data Type Configuration
(Input Parameter A)............................................................................................................................ 73
Table 19. Input Data Format Configuration
(Input Parameter B)............................................................................................................................ 73
Table 20. Input SCLK Polarity Configuration
(Input Parameter C) ........................................................................................................................... 75
Table 21. Input FIFO Setup Configuration
(Input Parameter D) ........................................................................................................................... 75
Table 22. Output Clock Configuration
(Parameter A)..................................................................................................................................... 76
Table 23. Output Data Format Configuration
(Parameter B)..................................................................................................................................... 76
Table 24. Output MCLK Configuration
(Parameter C) .................................................................................................................................... 77
Table 25. Output SCLK Configuration
(Parameter D) .................................................................................................................................... 77
Table 26. Output SCLK Polarity Configuration
(Parameter E)..................................................................................................................................... 77
Table 27. Example Values to be Sent to CS493XX After Download or Soft Reset ........................... 79
DS339PP4
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5 Page 
CS49300 Family DSP
A1:0
D A T A 7 :0
CS
R/W
DS
Tm ah
Tmas
Tm rw su
Tm dhr
Tmdd
Tm cdr
Tm rpw
Tm dis
Tm rd
Figure 5. Motorola® Parallel Host Mode Read Cycle
Tm rw hld
Tm rdtw
A1:0
Tm as
DA T A7:0
CS
R /W
DS
Tm ah
Tm d su
Tm dhw
Tm cdw
Tm rwsu
Tm wpw
Tm w d
Tm rw hld
Tm w trd
Figure 6. Motorola® Parallel Host Mode Write Cycle
DS339PP4
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| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet CS49330.PDF ] | |
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