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PDF CS4952 Data sheet ( Hoja de datos )
| Número de pieza | CS4952 | |
| Descripción | NTSC/PAL Digital Video Encoder | |
| Fabricantes | Cirrus Logic | |
| Logotipo |  |
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CS4952/53
NTSC/PAL Digital Video Encoder
Features
l Simultaneous composite and S-video output
l Supports RS170A and CCIR601 composite
output timing
l Multi-standard support for NTSC-M, PAL (B, D,
G, H, I, M, N, Combination N)
l Optional progressive scan @ MPEG2 field rates
l CCIR656 input mode supporting EAV/SAV
codes and CCIR601 Master/Slave input modes
l Stable color subcarrier for MPEG2 systems
l NTSC closed caption encoder with interrupt
l Supports Macrovision copy protection in
CS4953 version
l Host interface configurable for parallel or I2C
compatible operation
l General purpose input and output pins
l Individual DAC power-down capability
l On-chip voltage reference generator
l On-chip color bar generator
l +5 volt only, CMOS, low power modes, tri-state
DACs
Description
The CS4952/3 provides full conversion from YCbCr or
YUV digital video formats into NTSC & PAL Composite
and Y/C (S-video) analog video. Input formats can be
27 MHz 8-bit YUV, 8-bit YCbCr, or CCIR656 with sup-
port for EAV/SAV codes. Output video can be formatted
to be compatible with NTSC-M, or PAL B,D,G,H,I,M,N,
and Combination N systems. Also supported is NTSC
line 21 and line 284 closed captioning encoding.
Four 9-bit DACs provide two channels for an S-Video out-
put port and two composite video outputs. 2x oversampling
reduces the output filter requirements and guarantees
no DAC related modulation components within the spec-
ified bandwidth of any of the supported video standards.
Parallel or high speed I2C compatible control interfaces
are provided for flexibility in system design. The parallel
interface doubles as a general purpose I/O port when the
CS4952/3 is in I2C mode to help conserve valuable
board area.
ORDERING INFORMATION
CS4952/3-CL 44 pin PLCC
CS4952/3-CQ 44 pin TQFP
CLK
SCL
SDA
PDAT[7:0]
RD*
WR*
8
I 2C
Interface
Host
Parallel
Interface
Control
Registers
ADDR
XTAL
Color Sub-carrier
Synthesizer
VAA
Output
Interpolate
LPF
Chroma Amplifier
Chroma Modulate
Σ
Burst Insert
Chroma Interpolate
9-Bit
DAC
9-Bit
DAC
9-Bit
DAC
9-Bit
DAC
C
CVBS37
CVBS75
Y
8
VD[7:0]
Video
Formatter
U, V
Y
LPF
Luma Delay
HSYNC*
VSYNC*
FIELD
INT
RESET*
Video Timing
Generator
Luma Amplifier
Sync Insert
Output
Interpolate
LPF
GND
Voltage
Reference
Current
Reference
TEST
VREFIN
VREFOUT
ISET
Preliminary Product Information
This document contains information for a new product.
Cirrus Logic reserves the right to modify this product without notice.
Cirrus Logic, Inc.
Crystal Semiconductor Products Division
P.O. Box 17847, Austin, Texas 78760
(512) 445 7222 FAX: (512) 445 7581
http://www.crystal.com
Copyright © Cirrus Logic, Inc. 1997
(All Rights Reserved)
OCT ‘97
DS223PP2
1
1 page  
CS4952/53
D.C. CHARACTERISTICS: (TA=25 C; VAA = 5 V; GND = 0 V.)
Parameter
Symbol
Digital Inputs
High Level Input Voltage
High Level Input Voltage
V [7:0], PDAT [7:0],
HSYNC/VSYNC/FIELD/CLKIN
I2C
VIH
VIH
Low Level Input Voltage
All Inputs VIL
Input Leakage Current
Digital Inputs -
Digital Outputs
High Level Output Voltage
Io = -4mA VOH
Low Level Output Voltage
Io = 4mA VOL
Low Level Output Voltage
SDA pin only, Io = 6mA VOL
Output Leakage Current
High-Z Digital Outputs -
Analog Outputs
Full Scale Output Current
CVBS37/Y/C (Note 1) IO37
Full Scale Output Current
CVBS75 (Note 1) IO75
LSB Current
CVBS37/Y/C (Note 1) IB37
LSB Current
CVBS75 (Note 1) IB35
DAC-to-DAC Matching
MAT
Output Compliance
VOC
Output Impedance
ROUT
Output Capacitance
COUT
DAC Output Delay
ODEL
DAC Rise/Fall Time
(Note 2) TRF
Voltage Reference
Reference Voltage Output
VOV
Reference Input Current
IVC
Power Supply
Supply Voltage
VAA
Supply Current
All DACs on
CVBS75/CVGS37 only
CVBS75 only
IAA1
IAA2
IAA3
Min
2.0
0.7VAA
-0.3
-10
2.4
-
-
-10
32.9
16.4
64.5
32.2
-
0
-
-
-
-
1.198
-
4.75
-
-
-
Typ Max Units
- VAA+0.3 V
- -V
- 0.8 V
- +10 µA
- VAA V
- 0.4 V
- 0.4 V
- +10 µA
34.7
17.3
68
34
2
-
15
-
4
2.5
36.5
18.2
71.5
35.8
-
+1.4
-
30
12
5
mA
mA
µA
µA
%
V
kΩ
pF
ns
ns
1.232
-
1.272
10
V
µA
5 5.25 V
180 200 mA
110 - mA
75 - mA
Notes: 1. Output current levels with ISET = 10 kΩ, VREFIN = 1.232 V.
2. Times for black-to-white level and white-to-black level transitions.
DS223PP2
5
5 Page 
CS4952/53
INTRODUCTION
The CS4952/3 is a complete multi-standard digital
video encoder implemented in current 5-volt only
CMOS technology. CCIR601 or CCIR656 compli-
ant digital video input can be converted into
NTSC-M, PAL B, PAL D, PAL G, PAL H, PAL I,
PAL M, PAL N, or PAL N Argentina-compatible
analog video. The CS4952/3 is designed to connect
to MPEG1 and MPEG2 digital video decompres-
sors without glue logic.
Two 9-bit DAC outputs provide high quality
S-Video analog output while two other 9-bit DACs
simultaneously generate composite analog video.
The CS4952/3 will accept 8-bit YCbCr or 8-bit
YUV input data.
The CS4952/3 is completely configured and con-
trolled via an 8-bit host interface port or an I2C
compatible serial interface. This host port provides
access and control of all CS4952/3 options and fea-
tures like closed caption insertion, interrupts, etc.
In order to lower the end user set-top overall sys-
tem costs, the CS4952/3 provides an internal volt-
age reference which eliminates the requirement for
an external discrete 3-pin voltage reference.
FUNCTIONAL DESCRIPTION
In the following subsections, the functions of the
CS4952/3 will be described. The descriptions refer
to the block diagram on the cover page.
Video Timing Generator
All timing generation is accomplished via a
27 MHz input applied to the CLK pin. The
CS4952/3 can also accept an optional color burst
crystal on the ADDR & XTAL pins. See section:
Color Subcarrier Synthesizer (page 12), for further
details.
The Video Timing Generator is responsible for or-
chestrating most all of the other modules in the de-
vice. It works in harmony with external sync input
timing or by providing external sync timing out-
puts. It automatically disables color burst on appro-
priate scan lines and generates serration and
equalization pulses on appropriate scan lines.
The CS4952/3 is designed to function as a video
timing master or video timing slave. In both Master
and Slave Modes, all timing is sampled and assert-
ed with the rising edge of the CLK pin.
In most cases the CS4952/3 will serve as the video
timing master. The master timing cannot be exter-
nally altered other than through the host interface
by changing the video display modes: PAL or
NTSC and Progressive Scan. HSYNC, VSYNC
and FIELD are configured as outputs for Master
Mode. HSYNC can also be defined as a composite
blanking output signal in Master Mode. Exact hor-
izontal and vertical display timing is addressed in
section: Operational Description (page 14).
In Slave Mode HSYNC and VSYNC are config-
ured as input pins and are used to initialize inde-
pendent vertical and horizontal timing generators
upon their respective falling edges. FIELD remains
an output in Slave Mode.
The CS4952/3 also provides a CCIR-656 Slave
Mode where the video input stream contains EAV
and SAV codes. In this case, proper HSYNC
VSYNC timing is extracted automatically without
aid from any inputs other than the V [7:0].
CCIR-656 input data is sampled with the leading
edge of CLK. Slave Mode vertical and horizontal
timing derived via CCIR-656 or external hardware
must be equivalent to timing generated by the
CS4952/3 in Master Mode.
Video Input Formatter
The video input formatter translates YCbCr input
data into YUV information, if necessary, and splits
the luma and chroma information for filtering, scal-
ing, and modulation.
DS223PP2
11
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet CS4952.PDF ] | |
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