|
|
PDF CS5101EN14 Data sheet ( Hoja de datos )
| Número de pieza | CS5101EN14 | |
| Descripción | Secondary Side Post Regulator for AC/DC and DC/DC Multiple Output Converters | |
| Fabricantes | Cherry Semiconductor Corporation | |
| Logotipo |  |
|
Hay una vista previa y un enlace de descarga de CS5101EN14 (archivo pdf) en la parte inferior de esta página. Total 7 Páginas | ||
|
No Preview Available !
CS5101
Secondary Side Post Regulator for AC/DC
and DC/DC Multiple Output Converters
Description
Features
The CS5101 is a bipolar monolithic
secondary side post regulator
(SSPR) which provides tight regula-
tion of multiple output voltages in
AC-DC or DC-DC converters.
Leading edge pulse width modula-
tion is used with the CS5101.
The CS5101 is designed to operate
over an 8V to 45V supply voltage
(VCC) range and up to a 75V drive
voltage (VC).
The CS5101 features include a totem
pole output with 1.5A peak output
current capability, externally pro-
grammable overcurrent protection,
an on chip 2% precision 5V refer-
ence, internally compensated error
amplifier, externally synchronized
switching frequency, and a power
switch drain voltage monitor. It is
available in a 14 lead plastic DIP or
a 16 lead wide body SO package.
Application Diagram
VSY
1
TR
CR4 3
Q1
6
R5 R6
L1
4
5
CR5
R10 VOUT
R8 R11 R13
+ C6
R9 R12 R14
CR1
R1 R2
CR3
R3 CR2
+
C1
C2 R4
C3
VSYNC
VD
VCC CS5101 VC
VREF SSPR VG
LGnd
PGnd
VFB IS COMP
COMP
RAMP
IS-
IS+
2
CR
C5
R7
C4
Gnd
s 1.5A Peak Output
(Grounded Totem Pole)
s 8V to 75V Gate Drive Voltage
s 8V to 45V Supply Voltage
s 300ns Propagation Delay
s 1% Error Amplifier
Reference Voltage
s Lossless Turn On and
Turn Off
s Sleep Mode: < 100µA
s Overcurrent Protection with
Dedicated Differential Amp
s Synchronization to External
Clock
s External Power Switch
Drain Voltage Monitor
Package Options
14L PDIP
SYNC 1
VCC
VREF
LGnd
VFB
COMP
RAMP
VD
VC
VG
PGnd
IS COMP
IS-
IS+
16L SO Wide
SYNC 1
VCC
VREF
DGnd
VD
VC
VG
PGnd
AGnd
VFB
COMP
RAMP
PGnd
IS COMP
IS-
IS+
Rev. 3/31/97
Cherry Semiconductor Corporation
2000 South County Trail, East Greenwich, RI 02818
Tel: (401)885-3600 Fax: (401)885-5786
Email: [email protected]
Web Site: www.cherry-semi.com
1 A ¨ Company
1 page  
Circuit Description: continued
Theory of Operation
The CS5101 is designed to regulate voltages in multiple
output power supplies. Functionally, it is similar to a
magnetic amplifier, operating as a switch with a delayed
turn-on. It can be used with both single ended and dual
ended topologies.
The VFB voltage is monitored by the error amplifier EA. It
is compared to an internal reference voltage and the
amplified differential signal is fed through an inverting
amplifier into the buffer, BUF. The buffered signal is com-
pared at the PWM comparator with the ramp voltage
generated by capacitor CR. When the ramp voltage VR,
exceeds the control voltage VC, the output of the PWM
comparator goes high, latching its state through the
LATCH, the output stage transistor Q1 turns on, and the
external power switch, usually an N-FET, turns on.
SYNC Function
The SYNC circuit is activated at time t1 (Figure 1) when
the voltage at the SYNC pin exceeds the threshold level
(2.5V) of the SYNC comparator. The external ramp capac-
itor CR is allowed to charge through the internal current
source I (200µA). At time t2, the ramp voltage intersects
with the control voltage VC and the output of the PWM
comparator goes high, turning on the output stage and
the external power switch. At the same time, the PWM
comparator is latched by the RS latch, LATCH.
VSY
1 0V
2
VSY + VD
3 0V
VSY
4 0V
VSY Ð VOUT
0V
5
VSY + VC
6 0V
Ground Level
(Gate doesn't go
below Gnd)
t1 t2 t3
t4 t1
VD
VOUT + VD
VD
VSY
VC
VRAMP
VDS
VS
VL1
VG
The logic state of the LATCH can be changed only when
both the voltage level of the trailing edge of the power
pulse at the SYNC pin is less than the threshold voltage of
the SYNC comparator (2.5V) and the RAMP voltage is
less than the threshold voltage of the RAMP comparator
(1.65V). On the negative going transition of the secondary
side pulse VSY, gate G2 output goes high, resetting the
latch at time t3. Capacitor CR is discharged through tran-
sistor Q4. CRÕs output goes low disabling the output stage,
and the external power switch (an N-FET) is turned off.
RAMP Function
The value of the ramp capacitor CR is based on the
switching frequency of the regulator and the maximum
duty cycle of the secondary pulse VSY.
If the RAMP pin is pulled externally to 0.3V or below, the
SSPR is disabled. Current drawn by the IC is reduced to
less than 100µA, and the IC is in SLEEP mode.
FAULT Function
The voltage at the VCC pin is monitored by the undervolt-
age lockout comparator with hysteresis. When VCC falls
below the UVL threshold, the 5V reference and all the cir-
cuitry running off of it is disabled. Under this condition
the supply current is reduced to less than 500µA.
The VCC supply voltage is further monitored by the
VCC_OK comparator. When VCC is reduced below
VREF - 0.7V, a fault signal is sent to gate G1. This fault sig-
nal, which determines if VCC is absent, works in conjunc-
tion with the ramp signal to disable the output, but only
after the current cycle has finished and the RS latch is reset.
Therefore this fault will not cause the output to turn off
during the middle of an on pulse, but rather will utilize
lossless turn-off. This feature protects the FET from over-
voltage stress. This is accomplished through gate G1 by
driving transistor Q4 on.
An additional fault signal is derived from the REF_OK
comparator. VREF is monitored so to disable the output
through gate G1 when the VREF voltage falls below the
OK threshold. As in the VCC_OK fault, the REF_OK fault
disables the output after the current cycle has been com-
pleted. The fault logic will operate normally only when
VREF voltage is within the specification limits of REF_OK.
DRAIN Function
Figure 1. Waveforms for CS5101. The number to the left of each curve
refers to a node on the Application Diagram.
The drain pin, VD monitors the voltage on the drain of the
power switch and derives energy from it to keep the out-
put stage in an off state when VC or VCC is below the min-
imum specified voltage.
5
5 Page | ||
| Páginas | Total 7 Páginas | |
| PDF Descargar | [ Datasheet CS5101EN14.PDF ] | |
Hoja de datos destacado
| Número de pieza | Descripción | Fabricantes |
| CS5101EN14 | Secondary Side Post Regulator for AC/DC and DC/DC Multiple Output Converters | Cherry Semiconductor Corporation |
| Número de pieza | Descripción | Fabricantes |
| SLA6805M | High Voltage 3 phase Motor Driver IC. |
 Sanken |
| SDC1742 | 12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters. |
 Analog Devices |
|
DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares, |
| DataSheet.es | 2020 | Privacy Policy | Contacto | Buscar |