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CS51033YD8 데이터시트 PDF




Cherry Semiconductor Corporation에서 제조한 전자 부품 CS51033YD8은 전자 산업 및 응용 분야에서
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부품번호 CS51033YD8 기능
기능 Fast PFET Buck Controller Does Not Require Compensation
제조업체 Cherry Semiconductor Corporation
로고 Cherry Semiconductor Corporation 로고


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CS51033YD8 데이터시트, 핀배열, 회로
CS51033
Fast PFET Buck Controller
Does Not Require Compensation
Description
Features
The CS51033 is a switching con-
troller for use in DC-DC converters.
It can be used in the buck topology
with a minimum number of exter-
nal components. The CS51033 con-
sists of a 1.0A power driver for con-
trolling the gate of a discrete P-
channel transistor, fixed frequency
oscillator, short circuit protection
timer, programmable soft start, pre-
cision reference, fast output voltage
monitoring comparator, and output
stage driver logic with latch.
The high frequency oscillator
allows the use of small inductors
and output capacitors, minimizing
PC board area and systems cost.
The programmable soft start
reduces current surges at start up.
The short circuit protection timer
significantly reduces the PFET duty
cycle to approximately 1/30 of its
normal cycle during short circuit
conditions.
The CS51033 is available in 8L SO
and 8L PDIP plastic packages.
s 1A Totem Pole Output
Driver
s High Speed Oscillator
(700kHz max)
s No Stability
Compensation Required
s Lossless Short Circuit
Protection
s 2% Precision Reference
s Programmable Soft Start
Typical Application Diagram
3.3VIN
CIN
100µF
RC D4
101N5818
D2
1N4148
D3
1N4148
C1
0.1µF
C2 C3 COSC
1µF 100µF 150pF
VC
VCC
VGATE
U1
CS51033
COSC
VFB
RG
10
0.01µF
IRF 7404
4.7µH
Gnd CS
PGnd
CS
0.1µF
100
.1µF
D1
1N5821
C0 C4
100µF 0.1µF
1.5VOUT
@3Amp
100µF
Gnd
NOTE: Capacitors C2, C3 and C4 are low ESR tantalum
caps used for noise reduction.
RA
1.5k
RB
300
Gnd
Package Options
8 Lead SO Narrow & PDIP
VGATE 1
PGnd
COSC
Gnd
VC
CS
VCC
VFB
Rev. 2/13/98
Cherry Semiconductor Corporation
2000 South County Trail, East Greenwich, RI 02818
Tel: (401)885-3600 Fax: (401)885-5786
Web Site: www.cherry-semi.com
1 A ® Company




CS51033YD8 pdf, 반도체, 판매, 대치품
Block Diagram
COSC
VCC
CS
VCC
IC
7IC
Oscillator
Comparator
A1 G1
VGATE
Flip-Flop
RQ
VC
RG
VGATE
1.5V
2.5V
F2
G2 S Q
VFB
Comparator
-
A6 1.25V
+
PGnd
VFB
VCC
IT
G4
G3
CS
Comparator
A2
+
Hold
Off
Comp
-
0.7V
-
Fault
Comp
+
1.15V
CS Charge
Sense
Comparator
A4
RQ
2.3V
IT IT
55 5
1.5V
2.5V
F1
G5 S Q
Slow Discharge
Flip-Flop
A3
2.4V
+ Slow Discharge
Comparator
Gnd
Figure 1: Block Diagram for CS51033
Circuit Description
Theory of Operation
Control Scheme
The CS51033 monitors the output voltage to determine
when to turn on the PFET. If VFB falls below the internal ref-
erence voltage of 1.25V during the oscillator’s charge cycle,
the PFET is turned on and remains on for the duration of the
charge time. The PFET gets turned off and remains off dur-
ing the oscillator’s discharge cycle time with the maximum
duty cycle to 80%. It requires 7mV typical, and 20mV maxi-
mum ripple on the VFB pin is required to operate. This
method of control does not require any loop stability com-
pensation.
Startup
The CS51033 has an externally programmable soft start fea-
ture that allows the output voltage to come up slowly, pre-
venting voltage overshoot on the output.
At startup, the voltage on all pins is zero. As VCC rises, the
VC voltage along with the internal resistor RG keeps the
PFET off. As VCC and VC continue to rise, the oscillator
capacitor (COSC ) and the Soft start/Fault Timing capacitor
(CS) charges via internal current sources. COSC gets charged
by the current source IC and CS gets charged by the IT
source combination described by:
( )ICS = IT -
IT
55
+
IT
5
The internal Holdoff Comparator ensures that the external
PFET is off until VCS > 0.7V preventing the GATE flip-flop
(F2) from being set. This allows the oscillator to reach its
operating frequency before enabling the drive output. Soft
start is obtained by clamping the VFB comparator’s (A6) ref-
erence input to approximately 1/2 of the voltage at the CS
pin during startup, permitting the control loop and the out-
put voltage to slowly increase. Once the CS pin charges
above the Holdoff Comparator trip point of 0.7V, the low
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CS51033YD8 전자부품, 판매, 대치품
Applications Information: continued
to rise slowly and finally it controls the Hiccup short circuit
protection circuitry. This function reduces the PFET's duty
cycle to 2% of the CS period.
The most important consideration in calculating CS is that
it’s voltage does not reach 2.5V (the voltage at which the
fault detect circuitry is enabled) before VFB reaches 1.15V
otherwise the power supply will never start.
For this circuit
TFAULT = 0.1 × 10-6 × 1.55 × 105 = 0.0155
A larger value of CS will increase the fault time out time but
will also increase the soft start time.
8) Input Capacitor.
If the VFB pin reaches 1.15V the fault timing comparator will
discharge CS and the supply will not start. For the VFB volt-
age to reach 1.15V the output voltage must be at least 4 ×
1.15 = 4.6V.
If we choose an arbitrary startup time of 200µs we calculate
the value of CS from:
CS × 2.5V
T = ICHARGE
Use 0.1µf.
CS(min)
=
200µs × 264µA
2.5V
= 0.02µF
The fault time out time is the sum of the slow discharge
time the fast discharge time and the recharge time and is
obviously dominated by the slow discharge time.
The first parameter is the slow discharge time, it is the time
for the CS capacitor to discharge from 2.4V to 1.5V and is
given by:
CS × (2.4V-1.5V)
TSLOWDISCHARGE = ΙDISCHARGE
Where IDISCHARGE is 6µA typical.
TSLOWDISCHARGE = CS × 1.5V × 105
The fast discharge time occurs when a fault is first detected.
The CS capacitor is discharged from 2.5V to 2.4V.
TFASTDISCHARGE =
CS × (2.5V - 2.4V)
ΙFASTDISCHARGE
The input capacitor reduces the peak currents drawn from
the input supply and reduces the noise and ripple voltage
on the VCC and VC pins. This capacitor must also ensure
that the VCC remains above the UVLO voltage in the event
of an output short circuit. CIN should be a low ESR capacitor
of at least 100µf. A ceramic surface mount capacitor should
also be connected between VCC and ground to prevent
spikes.
9) MOSFET Selection
The CS51033 drive a P-channel MOSFET. The VGATE pin
swings from Gnd to VC. The type of PFET used depends on
the operating conditions but for input voltages below 7V a
logic level FET should be used.
Choose a PFET with a continuous drain current (Id) rating
greater than the maximum output current. RDS(on) should be
less than
RDS < =
0.6V
IOUT(max)
167m
The Gate-to-Source voltage VGS and the Drain-to Source
Breakdown Voltage should be chosen based on the input
supply voltage.
The power dissipation due to the conduction losses is given
by:
PD = OUT2 × RDS(on) × D
The power dissipation due to the switching losses is given
by:
Where IFASTDISCHARGE is 66µA typical.
TFASTDISCHARGE = CS × 1515
The recharge time is the time for CS to charge from 1.5V to
2.5V.
TCHARGE
=
CS
× (2.5V-1.5V)
ΙCHARGE
Where ICHARGE is 264µA typical.
TCHARGE = CS × 3787
The fault time out time is given by:
TFAULT = CS × (3787 + 1515 + 1.5 × 105)
TFAULT = CS × 1.55 × 105
PD = 0.5 × VIN × IOUT × (TRr + TF) × FSW
Where tr =Rise Time and tf= Fall Time.
10) Diode Selection.
The flyback or catch diode should be a Schottky diode
because of it’s fast switching ability and low forward volt-
age drop. The current rating must be at least equal to the
maximum output current. The breakdown voltage should
be at least 20V for this 12V application.
The diode power dissipation is given by:
PD = IOUT × VD × (1-DMIN)
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