Datasheet.kr   

CS5106LSW24 데이터시트 PDF




Cherry Semiconductor Corporation에서 제조한 전자 부품 CS5106LSW24은 전자 산업 및 응용 분야에서
광범위하게 사용되는 반도체 소자입니다.


 

PDF 형식의 CS5106LSW24 자료 제공

부품번호 CS5106LSW24 기능
기능 Multi-Feature/ Synchronous plus Auxiliary PWM Controller
제조업체 Cherry Semiconductor Corporation
로고 Cherry Semiconductor Corporation 로고


CS5106LSW24 데이터시트 를 다운로드하여 반도체의 전기적 특성과 매개변수에 대해 알아보세요.



전체 12 페이지수

미리보기를 사용할 수 없습니다

CS5106LSW24 데이터시트, 핀배열, 회로
CS5106
Multi-Feature, Synchronous plus Auxiliary
PWM Controller
Description
Features
The CS5106 is a fixed frequency,
current mode controller with one
single NFET driver and one dual
FET, synchronous driver. The syn-
chronous driver allows for
increased efficiency of the main iso-
lated power stage and the single
driver allows the designer to devel-
op auxiliary supplies for controller
power as well as secondary side
house keeping. In addition,
because the synchronous drivers
have programmable FET non-over-
lap, the CS5106 is an ideal con-
troller for soft-switched converter
topologies.
The CS5106 is specifically designed
for isolated topologies where speed,
flexibility, reduced size and
reduced component count are
requirements. The controller con-
tains the following features:
Undervoltage Shutdown,
Overvoltage Shutdown,
Programmable Frequency,
Programmable Synchronous Non-
Overlap Time, Master/Slave
Clocking with Frequency Range
Detection, Enable, Output
Undervoltage Protection with
Timer, 20mA 5V Output, 80ns
PWM propagation delay, and
Controlled Hiccup Mode.
The CS5106 has junction tempera-
ture and supply ranges of -40ûC to
125ûC and 9V to 16V respectively
and is available in the 24 lead SSOP
package.
Applications Diagram
48V to 3.3V Forward Converter with Synchronous Rectifiers
R27
R3
VIN SYNCIN
ENABLE
R1
R2
C4
C1 R4
C2
VAUXP
D1
VIN
T1
CS5106
UVSD
ENABLE
OVSD PROGRAM
C3 V5REF SYNC IN
OAM
SYNC OUT
OAOUT
FADJ
OUVDELAY DLYSET
ILIM1
ILIM2
RAMP1
RAMP2
VFB1
VSS
VFB2
GATE2B
VCC
GATE1
GATE2
VDD
VIN
C5 D2
R5
R8
Q2
Q1
VAUXS C7 R6
D6
R9
D3
C9 C10 R10
R11
R12
SYNCOUT
VAUXP
V5REF
D5
C6 R7
R24
D8
R15
R20
R16 C14 R17
R25 C13
R14
C8
TL431
R13
T4
CNY17-4
VAUXS
Q7
R26
VIN
T3
D4
R21
Q6
R23
D7
T2
C11
Q3
R22
Q4
R18
R19
L1
Q5
VMAIN
C12
s Programmable Fixed
Frequency
s Programmable FET Non-
overlap
s Enable Lead
s 12V Fixed Auxiliary
Supply Control
s Under and Overvoltage
Shutdown
s Output Undervoltage
Protection with Timer
s Master/Slave Clock
Syncing Capability
s Sync Frequency Range
Detection
s 80ns PWM Propagation
Delay
s 20mA 5V Reference
Output
s Small 24 lead SSOP
Package
s Controlled Hiccup Mode
Package Options
24 Lead SSOP
UVSD 1
OVSD
V5REF
OAM
OAOUT
OUVDELAY
ILIM1
RAMP1
VFB1
VSS
VCC
GATE1
ENABLE
PROGRAM
SYNCIN
SYNCOUT
FADJ
DLYSET
ILIM2
RAMP2
VFB2
GATE2B
GATE2
VDD
Rev. 10/27/98
Cherry Semiconductor Corporation
2000 South County Trail, East Greenwich, RI 02818
Tel: (401)885-3600 Fax: (401)885-5786
Web Site: www.cherry-semi.com
1 A ¨ Company




CS5106LSW24 pdf, 반도체, 판매, 대치품
Electrical Characteristics: TJ = -40¡C to 125¡C, VSS = 9 to 16V, V5REF ILOAD = 2mA, SYNCOUT Free Running, unless other-
wise specified. For All Specs: UVSD=6V, OVSD = 0V, ENABLE = 0V, ILIM(1,2) = 0,VFB(1,2) = 3V,RFADJ = RDLYSET = 27.4k½.
PARAMETER
TEST CONDITIONS
s Bias Supply Error Amplifier: continued
Output Low Sink Current
VSS > 12.6V. Measure OAOUT sink
current when OAOUT = 2.5V.
VSS Set Point
Large Signal Gain
Adjust VSS until OAOUT goes low.
(GBD)
Unity Gain Bandwidth
(GBD)
Common Mode Input Range (GBD)
MIN
TYP
3.0
11.60
15.00
1.00
20.0
12.25
1.00
MAX
UNIT
50.0
12.80
2.00
mA
V
V/mV
MHz
V
s VSS Voltage
VSS Reset Voltage
Toggle ENABLE between Gnd & VCC,
then adjust VSS from 2.0V-0.8V until
OAOUT goes high.
1.00 1.40 1.80
V
s Undervoltage Lockout
UVSD Turn On
Threshold Voltage
UVSD Turn Off Threshold
Voltage
Hysteresis
UVSD Input Bias Current
Adjust UVSD from 4.7V-5.3V
until GATE 1, 2 goes high.
Adjust UVSD from 5.1V-4.3V
until GATE 1, 2 goes low.
Turnon - Turnoff
Set UVSD=0V. Measure Current
out of UVSD lead.
4.80 5.00 5.10
V
4.45 4.70 4.95
V
0.20 0.27 0.40
V
0.20 0.50 µA
s Overvoltage Lockout
OVSD Threshold Voltage
OVSD Input Bias Current
Adjust OVSD from 4.7V-5.3V
until GATE 1, 2 goes low.
Set OVSD=0V. Measure Current out
of OVSD lead.
4.85
s ENABLE & PROGRAM
ENABLE Lead Output Current
PROGRAM Lead Output
Current
PROGRAM Threshold
Voltage
ENABLE Threshold Voltage
Measure current out of
ENABLE when ENABLE = 0V.
Measure current out of
PROGRAM when PROGRAM = 0V.
ENABLE = Gnd. Adjust
PROGRAM from 1.0V - 1.8V
until GATE 1, 2 goes high.
PROGRAM = Gnd.
Adjust ENABLE from 1.0V - 1.8V
until GATE 1, 2 goes high.
100.0
20.0
1.20
1.20
s Output Undervoltage Delay
OUVDELAY Charging
Current
OUVDELAY Latchoff Voltage
OUVDELAY Set Current
VFB1 Charge Threshold
VFB2 Charge Threshold
Set OUVDELAY = 1V, VFB1 = 4.4V
Measure OUVDELAY ICHARGE.
Toggle ENABLE between Gnd & VCC,
then adjust OUVDELAY from
4.7V - 5.3V until GATE 1, 2, goes low.
OUVDELAY = VOCLO + 50mV
Measure current into OUVDELAY.
VSS=1V. Toggle ENABLE between
Gnd & VCC, adjust VFB1 from 3.8V - 4.6V
until GATE 1, 2 goes low.
VSS = 1V. Toggle ENABLE between
Gnd & VCC, adjust VFB2 from 3.8V - 4.6V
until GATE 1, 2 goes low.
4
7.50
4.80
4.05
3.90
5.00
0.20
266.0
60.0
1.40
1.40
10.00
5.00
0.50
4.22
4.15
5.15
0.50
500.0
100.0
1.60
1.60
12.50
5.20
1.00
4.40
4.35
V
µA
µA
µA
V
V
µA
V
mA
V
V

4페이지










CS5106LSW24 전자부품, 판매, 대치품
Package Lead Description: continued
PACKAGE LEAD #
9
LEAD SYMBOL
VFB1
10 VSS
11 VCC
12 GATE1
13 Gnd
14 GATE2
15 GATE2B
16 VFB2
17 RAMP2
18 ILIM2
19 DLYSET
20 FADJ
21 SYNCOUT
22 SYNCIN
23 PROGRAM
24 ENABLE
FUNCTION
Voltage Feedback Lead for the Auxiliary PWM. A voltage which represents
the auxiliary power supply output voltage is fed to this lead. A voltage less
than RAMP1+0.13 on VFB1 will cause GATE1 to go low.
VSS power/feedback input lead. See VCC for description of power operation.
In addition, this lead is fed to a divide by ten resistor divider and compared to
1.2V nominal at the positive side of the error amplifier.
VCC power input lead. This input runs off a Zener referenced supply until
VSS > VCC. Then an internal diode which runs between VSS and VCC turns on
and all main power is derived from VSS.
Auxiliary PWM gate drive lead. This output normally drives the FET which
drives the auxiliary transformer.
Ground lead.
Synchronous PWM gate drive lead. This output normally drives the FET
which drives the main transformer.
Synchronous PWM gate drive lead. This output normally drives the FET for
the gate drive transformer used for synchronous rectification.
Voltage feedback lead for the synchronous PWM. A voltage which represents
the main power supply output voltage is fed to this lead. A voltage less than
RAMP2+0.13 on VFB2 will cause GATE2 to go low and GATE2B to go high.
Current ramp input lead for the synchronous PWM. A voltage which is linear
with respect to current in the primary side of the main trans former is usually
represented on this lead. A voltage exceeding VFB2 - 0.13 on RAMP2 will
cause GATE2 to go low and GATE2B to go high.
Pulse by pulse over current protection lead for the synchronous PWM. A volt-
age exceeding 1.2V nominal on ILIM2 will cause GATE2 to go low and GATE2B
to go high. A voltage exceeding 1.4V nominal on ILIM2 will cause GATE2 to go
low and GATE2B to go high for at least two clock cycles.
GATE2, GATE2B non-overlap time adjustment lead. A 27k½ resistor from
DLYSET to ground sets the non-overlap time to 45ns nominal.
Frequency adjustment lead. A 27k½ resistor from FADJ to ground sets the
clock frequency to 512kHz nominal.
Clock output lead. This is a 50% duty cycle, 1V to 5V pulse whose rising edge
is in phase with GATE1. This signal can be used to synchronize other power
supplies.
Clock synchronization lead. The internal clock frequency can be adjusted
+10%, -15% by the onset of positive edges of an external clock occurring on the
SYNCIN lead. If the external clock frequency is out side the internal clock fre-
quency by +25%, -35% the external clock is ignored and the internal clock free
runs.
ENABLE programming input. See ENABLE for programming states. PRO-
GRAM has at least 20µA min. of available source current.
PWM enable input. If PROGRAM is HIGH then a LOW on ENABLE will
allow GATE1, GATE2 and GATE2B to switch. If PROGRAM is LOW then a
HIGH on ENABLE will allow GATE1, GATE2 and GATE2B to switch. If
ENABLE is left floating, it will pull up to a HIGH level. ENABLE has at least
100µA (min) of available source current.
7

7페이지


구       성 총 12 페이지수
다운로드[ CS5106LSW24.PDF 데이터시트 ]

당사 플랫폼은 키워드, 제품 이름 또는 부품 번호를 사용하여 검색할 수 있는

포괄적인 데이터시트를 제공합니다.


구매 문의
일반 IC 문의 : 샘플 및 소량 구매
-----------------------------------------------------------------------

IGBT, TR 모듈, SCR 및 다이오드 모듈을 포함한
광범위한 전력 반도체를 판매합니다.

전력 반도체 전문업체

상호 : 아이지 인터내셔날

사이트 방문 :     [ 홈페이지 ]     [ 블로그 1 ]     [ 블로그 2 ]



관련 데이터시트

부품번호상세설명 및 기능제조사
CS5106LSW24

Multi-Feature/ Synchronous plus Auxiliary PWM Controller

Cherry Semiconductor Corporation
Cherry Semiconductor Corporation

DataSheet.kr       |      2020   |     연락처      |     링크모음      |      검색     |      사이트맵