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PDF CS5111YDWF24 Data sheet ( Hoja de datos )
| Número de pieza | CS5111YDWF24 | |
| Descripción | 1.4A Switching Regulator with 5V/ 100mA Linear Regulator with Watchdog/ RESET and ENABLE | |
| Fabricantes | Cherry Semiconductor Corporation | |
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CS5111
1.4A Switching Regulator with 5V, 100mA Linear
Regulator with Watchdog, RESET and ENABLE
Description
Features
The CS5111 is a dual output power sup-
ply integrated circuit. It contains a 5V
±2%, 100mA linear regulator, a watchdog
timer, a linear output voltage monitor to
provide a Power On Reset (POR) and a
1.4A current mode PWM switching reg-
ulator.
The 5V linear regulator is comprised of
an error amplifier, reference, and super-
visory functions. It has low internal sup-
ply current consumption and provides
1.2V (typical) dropout voltage at maxi-
mum load current.
The watchdog timer circuitry monitors
an input signal (WDI) from the micro-
processor. It responds to the falling
edge of this watchdog signal. If a correct
watchdog signal is not received within
the externally programmable time, a
reset signal is issued.
The externally programmable active
reset circuit operates correctly for an out-
put voltage (VLIN) as low as 1V. During
power up, or if the output voltage shifts
below the regulation limit, RESET tog-
gles low and remains low for the duration
of the delay after proper output voltage
regulation is restored. Additionally a reset
pulse is issued if the correct watchdog is
not received within the programmed
time. Reset pulses continue until the cor-
rect watchdog signal is received. The
reset pulse width and frequency, as well
as the Power On Reset delay, are set by
one external RC network.
The current mode PWM switching regu-
lator is comprised of an error amplifier
with selectable feedback inputs, a cur-
rent sense amplifier, an adjustable oscil-
lator, and a 1.4A output power switch
with anti-saturation control. The switch-
ing regulator can be configured in a
variety of topologies.
The CS5111 is load dump capable and
has protection circuitry which includes
overvoltage shutdown, current limit on
the linear and switcher outputs, and an
overtemperature limiter.
Block Diagram
s Linear Regulator
5V ± 2% @ 100mA
s Switching Regulator
1.4A Peak Internal
Switch
120kHz Maximum
Switching Frequency
5V to 26V Operating
Supply Range
s Smart Functions
Watchdog
RESET
ENABLE
s Protection
Overvoltage
Overtemperature
Current Limit
s 54V Peak Transient
Capability
VFB1
VFB2
SELECT
COMP
IBIAS
COSC
VREG
CDELAY
WDI
Multiplexer
Oscillator
Switcher
Error Amplifier
-
COMP
Logic
Base
Drive
Current Sense Amplifier
-
Switcher Shutdown
1.4A
VIN
VSW
Gnd
ENABLE
Over Voltage
Bandgap
Reference
Linear
Error Amplifier
-
1.25V
Current
Limit
Over
Temperature
VLIN
RESET &
Watchdog Timer
RESET
Package Option
24 Lead SO Wide
(Internally Fused Leads)
VIN 1
NC
NC
VSW
Gnd
Gnd
ENABLE
VREG
VLIN
IBIAS
Gnd
Gnd
Gnd Gnd
Gnd Gnd
VFB1
VFB2
SELECT
RESET
CDelay
WDI
COMP
COSC
Rev. 12/28/98
Cherry Semiconductor Corporation
2000 South County Trail, East Greenwich, RI 02818
Tel: (401)885-3600 Fax: (401)885-5786
Email: [email protected]
Web Site: www.cherry-semi.com
1 A ® Company
1 page  
VREG
Over Voltage
1.25V
IBIAS
RBIAS
64.9kΩ
Cdelay
WDI
Bandgap
Reference
Circuit Description
R1
Linear
Error
Q2
- Amplifier Q1
Current
Limit
Over
Temperature
RESET &
Watchdog Timer
Q3
R2
R3
R4
R5
VLIN
COUT = 100µF
ESR < 8Ω
RESET
Figure 2. Block diagram of 5V linear regulator portion of the CS5111.
5V Linear Regulator
The 5V linear regulator consists of an error amplifier,
bandgap voltage reference, and a composite pass transistor.
The 5V linear regulator circuitry is shown in Figure 2.
When an unregulated voltage greater than 6.6V is applied
to the VREG input, a 5V regulated DC voltage will be pre-
sent at VLIN. For proper operation of the 5V linear regula-
tor, the IBIAS lead must have a 64.9kΩ pull down resistor to
ground. A 100µF or larger capacitor with an ESR <8Ω
must be connected between VLIN and ground. To operate
the 5V linear regulator as an independent regulator (i.e.
separate from the switching supply), the input voltage
must be tied to the VREG lead.
As the voltage at the VREG input is increased, Q1 is turned
on. Q1 provides base drive for Q2 which in turn provides
base current for Q3. As Q3 is turned on, the output voltage,
VLIN, begins to rise as Q3’s output current charges the out-
put capacitor, COUT. Once VLIN rises to a certain level, the
error amplifier becomes biased and provides the appropri-
ate amount of base current to Q1. The error amplifier mon-
itors the scaled output voltage via an internal voltage
divider, R2 through R5, and compares it to the bandgap
voltage reference. The error amplifier output or error sig-
nal is an output current equal to the error amplifier’s input
differential voltage times the transconductance of the
amplifier. Therefore, the error amplifier varies the base
current to Q1, which provides bias to Q2 and Q3, based on
the difference between the reference voltage and the
scaled VLIN output voltage.
Using CDelay = 0.1µF and RBIAS = 64.9kΩ gives a time rang-
ing from 6.25ms to 11ms assuming ideal components. Based
on this, the software must be written so that the watchdog
arrives at least every 6.25ms. In practice, the tolerance of
CDelay and RBIAS must be taken into account when calculat-
ing the minimum watchdog time (tWDI).
VREG
RESET
WDI
VLIN
tPOR
Normal Operation
Figure 3. Timing diagram for normal regulator operation.
VREG
RESET
50% Duty
Cycle
WDI
Control Functions
The watchdog timer circuitry monitors an input signal
(WDI) from the microprocessor. It responds to the falling
edge of this watchdog signal which it expects to see within
an externally programmable time (see Figure 3).
The watchdog time is given by:
tWDI = 1.353 × CDelay RBIAS
VLIN
tPOR
AB
A: Watchdog waiting for B: RESET stays low for
low-going transition on tWDI time.
WDI
Figure 4. Timing diagram when WDI fails to appear within the preset
time interval, tWDI.
5
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| PDF Descargar | [ Datasheet CS5111YDWF24.PDF ] | |
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