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CS5124XD8 데이터시트 PDF




Cherry Semiconductor Corporation에서 제조한 전자 부품 CS5124XD8은 전자 산업 및 응용 분야에서
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부품번호 CS5124XD8 기능
기능 High Performance/ Integrated Current Mode PWM Controllers
제조업체 Cherry Semiconductor Corporation
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CS5124XD8 데이터시트, 핀배열, 회로
CS5124/6
High Performance, Integrated Current Mode
PWM Controllers
Description
Features
The CS5124/6 is a fixed frequency
current mode controller designed
specifically for DC-DC converters
found in the telecommunications
industry. The CS5124/6 integrates
many commonly required current
mode power supply features and
allows the power supply designer to
realize substantial cost and board
space savings. The product matrix is
as follows:
CS5124: 400kHz w/VBIAS Pin,
195mV first current sense threshold
CS5126: 200kHz w/SYNC Pin,
335mV first current sense threshold
The CS5124/6 integrates the follow-
ing features: Internal Oscillator, Slope
Compensation, Sleep On/Off, Under
Voltage Lock Out, Thermal
Shutdown, Soft Start Timer, Low
Voltage Current Sense for Resistive
Sensing, Second Current Threshold
for Pulse by Pulse Over Current
Protection, a Direct Optocoupler
Interface and Leading Edge Current
Blanking.
The CS5124/6 has supply range of
7.7V to 20V and is available in 8 pin
SO narrow package.
Applications Diagram
36-75VIN
L1
10µH
C1
0.1µF,
100V
R2
200k
R1
510k
C2
1.5µF,
100V
R5
17.4k
Q1
ZVN3310A D4
R4 BAS16LT1
10
C4
0.47µF,
25V
ENABLE
C9
1000pF
C7
0.1µF
VCC
Gnd
BIAS GATE
UVLO IS
CS5124
SS VFB
48VRTN
CTX15-14514
T1
D1
MBRD360CT
Q2
IRFR220
R8
0.39
R3
47
C3
.022µF
R7
R6 30.1k
1k
C6
U2 .01µF
C8
1000pF
TPS5908
R9
10.0k
5VOUT
C5
47µF,
10V
ISOLATED
RTN
48V to 5V, 1A flyback converter using the CS5124
s Line UVLO Monitoring
s Low Current Sense
Voltage for Resistive
Current Sensing
s External Synchronization
to Higher or Lower
Frequency Oscillator
(CS5126 Only)
s Bias for Start up Circuitry
(CS5124 Only)
s Thermal Shutdown
s Sleep On/Off Pin
s Soft Start Timer
s Leading Edge Blanking
s Direct Optocoupler
Interface
s 90ns Propagation Delay
s 35ns Driver Rise and Fall
Times
s Sleep Mode
Package Options
8 Lead SO Narrow
CS5124
VCC 1
Gnd
BIAS
UVLO
SS
GATE
ISENSE
VFB
VCC 1
CS5126
Gnd
UVLO
SYNC
SS
GATE
ISENSE
VFB
Rev. 3/12/99
Cherry Semiconductor Corporation
2000 South County Trail, East Greenwich, RI 02818
Tel: (401)885-3600 Fax: (401)885-5786
Web Site: www.cherry-semi.com
1 A ® Company




CS5124XD8 pdf, 반도체, 판매, 대치품
Electrical Characteristics: -40°C TJ 125°C, -40°C TA 105°C, 7.60V VCC 20V, UVLO = 3.0V, ISENSE = 0V,
CV(CC) = 0.33µF, CGATE = 1nF (ESR = 10), CSS = 470pF CV(FB) = 100pF, unless otherwise stated.
PARAMETER
s Voltage Feedback
VFB Pull-up Res.
VFB Clamp Voltage
VFB Clamp Voltage
VFB Fault Voltage Threshold
TEST CONDITIONS
CS5124 Only
CS5126 Only
MIN
2.9
2.63
2.40
460
TYP
4.3
2.90
2.65
490
MAX UNIT
8.1 k
3.15 V
2.90 V
520 mV
s Output Gate Drive
Maximum Sleep
Pull-down Voltage
GATE High (AC)
GATE Low (AC)
GATE High Clamp Voltage
Rise Time
Fall Time
VCC = 6.0V, IOUT = 1mA
Series resistance < 1(Note 1)
Series resistance < 1(Note 1)
VCC = 20V
Measure GATE rise time,
1V < GATE < 9V; VCC =12V
Measure GATE fall time,
9V > GATE > 1V; VCC = 12V
1.2
VCC-1
11.0
VCC-0.5
0.0
13.5
45
25
2.0
0.5
16.0
65
55
V
V
V
V
ns
ns
s Thermal Shutdown
Thermal Shutdown Temperature (Note 1) (GATE low)
Thermal Enable Temperature (Note 1) (GATE switching)
Thermal Hysteresis
(Note 1)
Notes
1. Not tested in production. Specification is guaranteed by design.
135 150 165 °C
100 125 150 °C
15 25 35 °C
Package Lead Description
PACKAGE LEAD #
8 Lead SO Narrow
CS5124 CS5126
11
2-
-3
32
44
55
66
77
88
LEAD SYMBOL
FUNCTION
VCC
BIAS
SYNC
UVLO
SS
VFB
ISENSE
GATE
Gnd
VCC Power Input Pin.
VCC Clamp Output Pin. This pin will control the gate of an N-channel MOS-
FET that in turn regulates VCC. This pin is internally clamped at 15V when
the IC is in sleep mode.
Clock Synchronization Pin. A positive edge will terminate the current PWM
cycle. Ground this pin when it is not used.
Sleep and under voltage lockout pin. A voltage greater than 1.8V causes the
chip to "wake up" however the GATE remains low. A voltage greater than
2.6V on this pin allows the output to switch.
Soft Start Capacitor Pin. A capacitor placed between SS and GROUND is
charged with 10µA and discharged with 10mA. The Soft Start capacitor con-
trols both soft-start time and hiccup mode frequency.
Voltage Feedback Pin. The collector of an optocoupler is typically tied to this
pin. This pin is pulled up internally by a 4.3kresistor to 5V and is clamped
internally at 2.9V(2.65V). If VFB is pulled > 4V, the oscillator is disabled and
GATE will stay high. If the VFB pin is pulled < 0.49V, GATE will stay low.
Current Sense Pin. This pin is connected to the current sense resistor on the
primary side. If VFB is floating, the GATE will go low if ISENSE = 195mV
(335mV). If ISENSE > 275mV (525mV), Soft Start will be initiated.
Gate Drive Output Pin. Capable of driving a 3nF load. GATE is nominally
clamped to 13.5V.
Ground Pin.
4

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CS5124XD8 전자부품, 판매, 대치품
Application Information: continued
The Line BIAS pin shows a significant change in the regu-
lated VCC voltage when sinking large currents. This will
show up as poor line regulation with a low value pull-up
resistor. Typical regulated VCC vs BIAS pin sink current is
shown in Figure 1.
the rising edge of the Gate is shown in Figure 4. When this
pin is held high or low the internal clock determines the
oscillator frequency.
SYNC
8.3 OSC
GATE
8.2
8.1 Figure 3. Synchronized Operation
8
7.9
5µ
10µA
20µA
50µA
100µA 200µA
Bias Current (IBIAS)
Figure 1. Regulated VCC vs BIAS Sink Current
Clock Synchronization Pin (CS5126 Only)
The CS5126 can be synchronized to signals ranging from
30% slower to several times faster than the internal oscilla-
tor frequency. If the part is synchronized to a fast signal,
maximum duty cycle will be reduced as the frequency
increases as shown in Figure 2.
140
130
120
110
100
90
80
70
200kHz
300kHz
400kHz
500kHz
600kHz
0.82
0.77
125°C
25°C
-40°C
Figure 4 : Typical Phase Lag between SYNC and GATE on.
Gate Drive
Rail to rail gate driver operation can be obtained (up to
13.5V) over a range of MOSFET input capacitance if the
gate resistor value is kept low. Figure 5 shows the high
gate drive level vs. the series gate resistance with VCC = 8V
driving an IRF220.
0.72
200kHz
300kHz 400kHz
Frequency
500kHz
600kHz
8.5
8
Figure 2: CS5126 Maximum Duty Cycle vs Frequency (Synchronized
Operation)
7.5
7
If the converter is initially free running and a sync signal is
applied, the current oscillator cycle will terminate and the
oscillator will lock on to the sync signal. The SYNC pin
works with a positive edge triggered signal. When the sync
signal transitions high the current PWM cycle terminates
and a new cycle begins as shown in Figure 3. The typical
phase lag between the rising edge of the SYNC signal and
6.5
6
0
0.3 0.5 2.5
5
Gate Resistor Value
11
Figure 5. Gate Drive vs Gate Resistor Driving an IRF220 (VCC = 8V)
7

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