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PDF CS5126XD8 Data sheet ( Hoja de datos )
| Número de pieza | CS5126XD8 | |
| Descripción | High Performance/ Integrated Current Mode PWM Controllers | |
| Fabricantes | Cherry Semiconductor Corporation | |
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CS5124/6
High Performance, Integrated Current Mode
PWM Controllers
Description
Features
The CS5124/6 is a fixed frequency
current mode controller designed
specifically for DC-DC converters
found in the telecommunications
industry. The CS5124/6 integrates
many commonly required current
mode power supply features and
allows the power supply designer to
realize substantial cost and board
space savings. The product matrix is
as follows:
CS5124: 400kHz w/VBIAS Pin,
195mV first current sense threshold
CS5126: 200kHz w/SYNC Pin,
335mV first current sense threshold
The CS5124/6 integrates the follow-
ing features: Internal Oscillator, Slope
Compensation, Sleep On/Off, Under
Voltage Lock Out, Thermal
Shutdown, Soft Start Timer, Low
Voltage Current Sense for Resistive
Sensing, Second Current Threshold
for Pulse by Pulse Over Current
Protection, a Direct Optocoupler
Interface and Leading Edge Current
Blanking.
The CS5124/6 has supply range of
7.7V to 20V and is available in 8 pin
SO narrow package.
Applications Diagram
36-75VIN
L1
10µH
C1
0.1µF,
100V
R2
200k
R1
510k
C2
1.5µF,
100V
R5
17.4k
Q1
ZVN3310A D4
R4 BAS16LT1
10Ω
C4
0.47µF,
25V
ENABLE
C9
1000pF
C7
0.1µF
VCC
Gnd
BIAS GATE
UVLO IS
CS5124
SS VFB
48VRTN
CTX15-14514
T1
D1
MBRD360CT
Q2
IRFR220
R8
0.39Ω
R3
47Ω
C3
.022µF
R7
R6 30.1k
1k
C6
U2 .01µF
C8
1000pF
TPS5908
R9
10.0k
5VOUT
C5
47µF,
10V
ISOLATED
RTN
48V to 5V, 1A flyback converter using the CS5124
s Line UVLO Monitoring
s Low Current Sense
Voltage for Resistive
Current Sensing
s External Synchronization
to Higher or Lower
Frequency Oscillator
(CS5126 Only)
s Bias for Start up Circuitry
(CS5124 Only)
s Thermal Shutdown
s Sleep On/Off Pin
s Soft Start Timer
s Leading Edge Blanking
s Direct Optocoupler
Interface
s 90ns Propagation Delay
s 35ns Driver Rise and Fall
Times
s Sleep Mode
Package Options
8 Lead SO Narrow
CS5124
VCC 1
Gnd
BIAS
UVLO
SS
GATE
ISENSE
VFB
VCC 1
CS5126
Gnd
UVLO
SYNC
SS
GATE
ISENSE
VFB
Rev. 3/12/99
Cherry Semiconductor Corporation
2000 South County Trail, East Greenwich, RI 02818
Tel: (401)885-3600 Fax: (401)885-5786
Email: [email protected]
Web Site: www.cherry-semi.com
1 A ® Company
1 page  
Block Diagram
VCC
UVLO
BIAS
(CS5124 ONLY)
SS
{CS5126 ONLY}
SYNC
VCC UVLO COMP
+
-
+
V 7.7 V/7.275V
LINE UVLO COMP
-
TSHUT
+
150°C/125°C
+
V
2.62 V/2.45V
REMOTE
(SLEEP) COMP
+
-
+
V 1.91 V/1.83V
VCC
LINE AMP -
+
+
2.0V V
2.9 R
R
VCC
G2 VREF = 5V
ENABLE
OSC
DIS
RAMP
RQ
F1
S
G1
-
V+REFOK
+
V
SOFT START LATCH
F2
G5 S Q
R
SET DOMAIN
-
+
SS COMP
V5REF
RESET DOMAIN
{85 mV/us}
170mV us
V5REF
10µA
G3
-
VFB COMP
+
+
V 490mV
PWM COMP -
+ +V
{125mV}
60mV
+
{525mV}
- 275mV
2ND ICOMP
+
V
{1/5}
1/10
÷
1000Ω
BLANKING
{2.65V}
2.90V
+
V
BLANK
V5REF
G6
+
275mV V
1.32V
+V
F3
SQ
R
DRIVER
V5REF
G7 4500Ω
SS AMP
+
-
GATE
VFB
ISENSE
Gnd
Theory of Operation
Powering the IC
10µA. As the capacitor charges, a buffered version of the
VCC can be powered directly from a regulated supply
and requires 500µA of start-up current. The CS5124/6
includes a line bias pin (BIAS) that can be used to control a
capacitor voltage appears on the VFB pin and the VFB volt-
age begins to rise. As VFB rises the duty cycle increases
until the supply comes into regulation.
series pass transistor for operation over a wide input volt-
age. The BIAS pin will control the gate voltage of an N-
channel MOSFET placed between VIN and VCC to regulate
VCC at 8V.
Soft Start
Soft Start is accomplished by clamping the VFB pin 1.32V
below the SS pin during normal start up and during restart
VCC and UVLO Pins
The UVLO pin has three different modes; low power shut-
down, Line UVLO, and normal operation. To illustrate
how the UVLO pin works; assume that VIN, as shown in
the application schematic, is ramped up starting at 0V with
the UVLO pin open. The SS and ISENSE pins also start at 0V.
While the UVLO is below 1.8V, the IC will remain in a low
after a fault condition. When the CS5124/6 starts, the Soft
Start capacitor is charged from a 10µA source from 0V to
4.9V. The VFB pin follows the Soft Start pin offset by –1.32V
until the supply comes into regulation or until the Soft
Start error amp is clamped at 2.9V (2.65V for the CS5126).
During fault conditions the Soft Start capacitor is dis-
charged at 10mA.
current sleep mode and the BIAS pin of the CS5124 is inter-
nally clamped to a maximum of 15V. When the voltage on
the UVLO pin rises to between 1.8V and 2.6V the reference
for the VCC UVLO is enabled and VCC is regulated to 8V by
the BIAS pin (CS5124 only), but the IC remains in a UVLO
state and the output driver does not switch. When the
UVLO pin exceeds 2.6V and the VCC pin exceeds 7.7V, the
GATE pin is released from a low state and can begin
switching based on the comparison of the ISENSE and VFB
pins. The Soft Start capacitor begins charging from 0V at
Fault Conditions
The CS5124/6 recognizes the following faults: UVLO off,
Thermal Shutdown, VREF(OK), and Second Current
Threshold. Once a fault is recognized, fault latch F2 is set
and the IC immediately shuts down the output driver and
discharges the Soft Start capacitor. Soft Start will begin
only after all faults have been removed and the Soft Start
capacitor has been discharged to less than 0.275V. Each
fault will be explained in the following sections.
5
5 Page | ||
| Páginas | Total 10 Páginas | |
| PDF Descargar | [ Datasheet CS5126XD8.PDF ] | |
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