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CS5132GDW24 데이터시트 PDF




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부품번호 CS5132GDW24 기능
기능 Dual Output CPU Buck Controller
제조업체 Cherry Semiconductor Corporation
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CS5132GDW24 데이터시트, 핀배열, 회로
CS5132
Dual Output CPU Buck Controller
Description
Features
The CS5132 is a dual output CPU
power supply controller. It con-
tains a synchronous dual NFET
buck controller utilizing the V2TM
control method to achieve the
fastest possible transient response
and best overall regulation. The
CS5132 also contains a second non-
synchronous NFET buck con-
troller. These synchronous and
non-synchronous buck regulators
are designed to power the core and
I/O logic of the latest high perfor-
mance CPUs. The CS5132 incorpo-
rates many additional features
required to ensure the proper
operation and protection of the
CPU and power system. The
CS5132 dual output provides the
industryÕs most highly integrated
solution, minimizing external com-
ponent count, total solution size,
and cost.
The CS5132 is specifically designed
to power IntelÕs Pentium¨ II pro-
cessor and includes the following
features: 5 bit DAC and fixed
1.23V reference, Power-Good out-
put, hiccup mode overcurrent pro-
tection, adaptive voltage position-
ing, and overvoltage protection.
The CS5132 will operate over an
8.4V to 14V range and is available
in 24 lead surface mount package.
Application Diagram
+3.3V (VI/O)
+5V
C3-C5
1200mF x 3
10V
PCB TRACE
(FreeCurrent
Sensing Element)
6.6mW
L2
3.5mH
C18-C21
1200mF
10V
x4
R2
510W
Q3
FS70VSJ-03
MBRD835L
D1
C17
R6
510W
0.1mF
R3
2K
1%
+12V +12V
C2
1mF
20 16
23 VID0 VCC1 VCC2
24 VID1
1 VID2
2 VID3
GATE(H)
GATE(L)
COMP2
17
19
13
3 VID4
15 GATE
51W
10
VFFB2
VFFB1
12 VOUT2
11 VFB2
VOUT1
PWRGD
14 COFF2
OVP
COMP1
8
6
22
21
5
7 VFB1
4
COFF1
LGnd
9
PGnd
18
C1
1mF
+5V
C6-C11
Q1
FS70VSJ-03
L1
1.2mH
1200mF x 6
10V
PCB TRACE (Free
Current Sensing
Element)
3.3mW
C23-C30
VCC(CORE)
1200mF x 8
10V
Q2
FS70VSJ-03
C12
0.1mF
C22
10K
100pF R7
R8
R1
510W R5
510W
C13
0.1mF
C15
680pF
C14
0.1mF
100W
R10
0.01mF
C25
R9
10K
R4
1.18K
1%
C16
390pF
5V/12V to 2V/16A for Pentium¨II VCC(CORE) , 5V/12V to 3.3V/8A for VI/O
V2 is a trademark of Switch Power, Inc.
Pentium is a registered trademark of Intel Corporation.
s Synchronous Switching
Regulator Controller (VCORE)
s Dual N-Channel MOSFET
Synchronous Buck Design
s V2TM Control Topology
s 200ns Transient Loop Response
s 5 bit DAC with 1% Tolerance
s Hiccup Mode Overcurrent
Protection
s 65ns adaptive FET Non-Overlap
Time
s Non-Synchronous Switching
Regulator Controller (VI/O)
s Single N-Channel MOSFET
buck design
s Adjustable Output with 2%
Tolerance
s System Power Management
Pentium¨ II System VCORE
and VI/O Controlled by
a Single IC
Power-Good Output
Monitors VCORE Switching
Regulator Output
OVP Signal Monitors VCORE
Switching Regulator Output
Package Options
24L SO Wide
VID2 1
VID3 2
VID4 3
COFF1 4
COMP1 5
VOUT1 6
VFB1 7
VFFB1 8
LGND 9
VFFB2 10
VFB2 11
VOUT2 12
24 VID1
23 VID0
22 PWRGD
21 OVP
20 VCC1
19 GATEL
18 PGND
17 GATEH
16 VCC2
15 GATE
14 COFF2
13 COMP2
Rev. 11/3/98
Cherry Semiconductor Corporation
2000 South County Trail, East Greenwich, RI 02818
Tel: (401)885-3600 Fax: (401)885-5786
Web Site: www.cherry-semi.com
1
A Company
¨




CS5132GDW24 pdf, 반도체, 판매, 대치품
Electrical Characteristics: 0ûC < TA < 70ûC; 0ûC < TJ < 125ûC; VOUT2 ² 3.5V, 9V ² VCC1 ² 14V, 9V ² VCC2 ² 14V; 2.0V DAC Code
(VID4= VID3 = VID2 = VID1 = 0, VID0 = 1), CGATE(H) = CGATE(L) = CGATE = 3.3nF, COFF = 390pF; Unless otherwise stated.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
s VCORE Switching Regulator Error Amplifier
VFB1 Bias Current
VFB1 = 0V
-1.0 0.1 1.0 µA
COMP1 Source Current
COMP1 = 1.2V to 3.6V; VFB1 = 1.9 V
15
30 60 µA
COMP1 Sink Current
COMP1=1.2V; VFB1 =2.1V;
30 60 120 µA
Open Loop Gain
CCOMP1 = 0.1µF
80 dB
Unity Gain Bandwidth
CCOMP1 = 0.1µF
20 kHz
PSRR @ 1kHz
CCOMP1 = 0.1µF
70 dB
s Voltage Identification DAC
Accuracy (all codes)
VID4 VID3 VID2 VID1 VID0
1 00 0 0
1 00 0 1
1 00 1 0
1 00 1 1
1 01 0 0
1 01 0 1
1 01 1 0
1 01 1 1
1 10 0 0
1 10 0 1
1 10 1 0
1 10 1 1
1 11 0 0
1 11 0 1
1 11 1 0
0 00 0 0
0 00 0 1
0 00 1 0
0 00 1 1
0 01 0 0
0 01 0 1
0 01 1 0
0 01 1 1
0 10 0 0
0 10 0 1
0 10 1 0
0 10 1 1
0 11 0 0
0 11 0 1
0 11 1 0
0 11 1 1
1 11 1 1
Line Regulation
Input Threshold
Measure VFB1 = COMP1,
25ûC ² TJ² 125ûC, VCC1 = VCC2 = 12V
-1.0
9V ² VCC1 ² 14V
VID4, VID3, VID2, VID1, VID0
3.489
3.390
3.291
3.192
3.093
2.994
2.895
2.796
2.697
2.598
2.499
2.400
2.301
2.202
2.103
2.054
2.004
1.955
1.905
1.856
1.806
1.757
1.707
1.658
1.608
1.559
1.509
1.460
1.410
1.361
1.311
1.225
1.00
3.525
3.425
3.325
3.225
3.125
3.025
2.925
2.825
2.725
2.625
2.525
2.425
2.325
2.225
2.125
2.075
2.025
1.975
1.925
1.875
1.825
1.775
1.725
1.675
1.625
1.575
1.525
1.475
1.425
1.375
1.325
1.250
0.01
1.25
1.0
3.560
3.459
3.358
3.257
3.156
3.055
2.954
2.853
2.752
2.651
2.550
2.449
2.348
2.247
2.146
2.096
2.045
1.995
1.944
1.894
1.843
1.793
1.742
1.692
1.641
1.591
1.540
1.490
1.439
1.389
1.338
1.275
2.40
%
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
%/V
V
4

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CS5132GDW24 전자부품, 판매, 대치품
Application Information
Theory Of Operation
V2TM Control Method
The V2TM method of control uses a ramp signal that is gen-
erated by the ESR of the output capacitors. This ramp is
proportional to the AC current through the main inductor
and is offset by the value of the DC output voltage. This
control scheme inherently compensates for variation in
either line or load conditions, since the ramp signal is gen-
erated from the output voltage itself. This control scheme
differs from traditional techniques such as voltage mode,
which generates an artificial ramp, and current mode,
which generates a ramp from inductor current.
Line and load regulation are drastically improved because
there are two independent voltage loops. A voltage mode
controller relies on a change in the error signal to compen-
sate for a deviation in either line or load voltage. This
change in the error signal causes the output voltage to
change corresponding to the gain of the error amplifier,
which is normally specified as line and load regulation.
A current mode controller maintains fixed error signal
under deviation in the line voltage, since the slope of the
ramp signal changes, but still relies on a change in the
error signal for a deviation in load. The V2TM method of
control maintains a fixed error signal for both line and load
variation, since the ramp signal is affected by both line and
load.
PWM
Comparator
C
Ð
GATE(H)
GATE(L)
COMP
Ramp Signal VFFB
Error
Amplifier Ð
Error
Signal
E
+
Figure 1: V2TM Control Diagram.
Output
Voltage
Feedback
VFB
Reference
Voltage
Constant Off-Time
To minimize transient response, the CS5132 uses a
Constant Off-Time method to control the rate of output
pulses. During normal operation, the Off-Time of the high
side switch is terminated after a fixed period, set by the
COFF capacitor. Every time the VFFB pin exceeds the COMP
pin voltage an Off-Time is initiated. To maintain regula-
tion, the V2TM Control Loop varies switch On-Time. The
PWM comparator monitors the output voltage ramp, and
terminates the switch On-Time.
Constant Off-Time provides a number of advantages.
Switch duty Cycle can be adjusted from 0 to 100% on a
pulse-by pulse basis when responding to transient condi-
tions. Both 0% and 100% Duty Cycle operation can be
maintained for extended periods of time in response to
Load or Line transients.
The V2TM control method is illustrated in Figure 1. The out-
put voltage is used to generate both the error signal and
the ramp signal. Since the ramp signal is simply the output
voltage, it is affected by any change in the output regard-
less of the origin of that change. The ramp signal also con-
tains the DC portion of the output voltage, which allows
the control circuit to drive the main switch to 0% or 100%
duty cycle as required.
A change in line voltage changes the current ramp in the
inductor, affecting the ramp signal, which causes the V2TM
control scheme to compensate the duty cycle. Since the
change in inductor current modifies the ramp signal, as in
current mode control, the V2TM control scheme has the
same advantages in line transient response.
A change in load current will have an affect on the output
voltage, altering the ramp signal. A load step immediately
changes the state of the comparator output, which controls
the main switch. Load transient response is determined
only by the comparator response time and the transition
speed of the main switch. The reaction time to an output
load step has no relation to the crossover frequency of the
error signal loop, as in traditional control methods.
The error signal loop can have a low crossover frequency,
since transient response is handled by the ramp signal
loop. The main purpose of this ÔslowÕ feedback loop is to
provide DC accuracy. Noise immunity is significantly
improved, since the error amplifier bandwidth can be
rolled off at a low frequency. Enhanced noise immunity
improves remote sensing of the output voltage, since the
noise associated with long feedback traces can be effective-
ly filtered.
Programmable Output
The CS5132 is designed to provide two methods for pro-
gramming the output voltage of the power supply. A five
bit on board digital to analog converter (DAC) is used to
program the output voltage within two different ranges.
The first range is 2.125V to 3.525V in 100mV steps, the sec-
ond is 1.325V to 2.075V in 50mV steps, depending on the
digital input code. If all five bits are left open, the CS5132
enters adjust mode. In adjust mode, the designer can
choose any output voltage by using resistor divider feed-
back to the VFB pin, as in traditional controllers. The
CS5132 is specifically designed to meet or exceed IntelÕs
Pentium¨ II specifications.
Error Amplifier
An inherent benefit of the V2TM control topology is that
there is no large bandwidth requirement on the error
amplifier design. The reaction time to an output load step
has no relation to the crossover frequency, since transient
response is handled by the ramp signal loop. The main
purpose of thisÓslowÓfeedback loop is to provide DC accu-
racy. Noise immunity is significantly improved, since the
error amplifier bandwidth can be rolled off at a low fre-
quency. Enhanced noise immunity improves remote sens-
ing of the output voltage, since the noise associated with
long feedback traces can be effectively filtered. The COMP
pin is the output of the error amplifier and a capacitor to
LGnd compensates the error amplifier loop. Additionally,
through the built-in offset on the PWM Comparator non-
inverting input, the COMP pin provides the hiccup timing
for the Over-Current Protection, the soft start function that
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부품번호상세설명 및 기능제조사
CS5132GDW24

Dual Output CPU Buck Controller

Cherry Semiconductor Corporation
Cherry Semiconductor Corporation

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