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PDF CS5132GDWR24 Data sheet ( Hoja de datos )
| Número de pieza | CS5132GDWR24 | |
| Descripción | Dual Output CPU Buck Controller | |
| Fabricantes | Cherry Semiconductor Corporation | |
| Logotipo |  |
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CS5132
Dual Output CPU Buck Controller
Description
Features
The CS5132 is a dual output CPU
power supply controller. It con-
tains a synchronous dual NFET
buck controller utilizing the V2TM
control method to achieve the
fastest possible transient response
and best overall regulation. The
CS5132 also contains a second non-
synchronous NFET buck con-
troller. These synchronous and
non-synchronous buck regulators
are designed to power the core and
I/O logic of the latest high perfor-
mance CPUs. The CS5132 incorpo-
rates many additional features
required to ensure the proper
operation and protection of the
CPU and power system. The
CS5132 dual output provides the
industryÕs most highly integrated
solution, minimizing external com-
ponent count, total solution size,
and cost.
The CS5132 is specifically designed
to power IntelÕs Pentium¨ II pro-
cessor and includes the following
features: 5 bit DAC and fixed
1.23V reference, Power-Good out-
put, hiccup mode overcurrent pro-
tection, adaptive voltage position-
ing, and overvoltage protection.
The CS5132 will operate over an
8.4V to 14V range and is available
in 24 lead surface mount package.
Application Diagram
+3.3V (VI/O)
+5V
C3-C5
1200mF x 3
10V
PCB TRACE
(FreeCurrent
Sensing Element)
6.6mW
L2
3.5mH
C18-C21
1200mF
10V
x4
R2
510W
Q3
FS70VSJ-03
MBRD835L
D1
C17
R6
510W
0.1mF
R3
2K
1%
+12V +12V
C2
1mF
20 16
23 VID0 VCC1 VCC2
24 VID1
1 VID2
2 VID3
GATE(H)
GATE(L)
COMP2
17
19
13
3 VID4
15 GATE
51W
10
VFFB2
VFFB1
12 VOUT2
11 VFB2
VOUT1
PWRGD
14 COFF2
OVP
COMP1
8
6
22
21
5
7 VFB1
4
COFF1
LGnd
9
PGnd
18
C1
1mF
+5V
C6-C11
Q1
FS70VSJ-03
L1
1.2mH
1200mF x 6
10V
PCB TRACE (Free
Current Sensing
Element)
3.3mW
C23-C30
VCC(CORE)
1200mF x 8
10V
Q2
FS70VSJ-03
C12
0.1mF
C22
10K
100pF R7
R8
R1
510W R5
510W
C13
0.1mF
C15
680pF
C14
0.1mF
100W
R10
0.01mF
C25
R9
10K
R4
1.18K
1%
C16
390pF
5V/12V to 2V/16A for Pentium¨II VCC(CORE) , 5V/12V to 3.3V/8A for VI/O
V2 is a trademark of Switch Power, Inc.
Pentium is a registered trademark of Intel Corporation.
s Synchronous Switching
Regulator Controller (VCORE)
s Dual N-Channel MOSFET
Synchronous Buck Design
s V2TM Control Topology
s 200ns Transient Loop Response
s 5 bit DAC with 1% Tolerance
s Hiccup Mode Overcurrent
Protection
s 65ns adaptive FET Non-Overlap
Time
s Non-Synchronous Switching
Regulator Controller (VI/O)
s Single N-Channel MOSFET
buck design
s Adjustable Output with 2%
Tolerance
s System Power Management
Pentium¨ II System VCORE
and VI/O Controlled by
a Single IC
Power-Good Output
Monitors VCORE Switching
Regulator Output
OVP Signal Monitors VCORE
Switching Regulator Output
Package Options
24L SO Wide
VID2 1
VID3 2
VID4 3
COFF1 4
COMP1 5
VOUT1 6
VFB1 7
VFFB1 8
LGND 9
VFFB2 10
VFB2 11
VOUT2 12
24 VID1
23 VID0
22 PWRGD
21 OVP
20 VCC1
19 GATEL
18 PGND
17 GATEH
16 VCC2
15 GATE
14 COFF2
13 COMP2
Rev. 11/3/98
Cherry Semiconductor Corporation
2000 South County Trail, East Greenwich, RI 02818
Tel: (401)885-3600 Fax: (401)885-5786
Email: [email protected]
Web Site: www.cherry-semi.com
1
A Company
¨
1 page  
Electrical Characteristics: 0ûC < TA < 70ûC; 0ûC < TJ < 125ûC; VOUT2 ² 3.5V, 9V ² VCC1 ² 14V, 9V ² VCC2 ² 14V; 2.0V DAC Code
(VID4= VID3 = VID2 = VID1 = 0, VID0 = 1), CGATE(H) = CGATE(L) = CGATE = 3.3nF, COFF = 390pF; Unless otherwise stated.
PARAMETER
Input Pull-up Resistance
Pull-up Voltage
TEST CONDITIONS
VID4, VID3, VID2, VID1, VID0
MIN
25
5.48
TYP
50
5.65
MAX
100
5.82
UNIT
k½
V
s GATE(H) and GATE(L)
High Voltage at 100mA
Low Voltage at 100mA
Rise Time
Fall Time
GATE(H) to GATE(L) Delay
GATE(L) to GATE(H) Delay
GATE pull-down
Measure VCC1/2 ÐGATE(L)/(H)
Measure GATE(L)/(H)
1.6V < GATE(H)/(L) < (VCC1/2 Ð 2.5V)
(VCC1/2 Ð 2.5V) > GATE(L)/(H) > 1.6V
GATE(H)<2V, GATE(L)>2V
30
GATE(L)<2V, GATE(H)>2V
30
Resistance to PGnd (Note 1)
20
1.2 2.1
1.0 1.5
40 80
40 80
65 100
65 100
50 115
V
V
ns
ns
ns
ns
k½
s VCORE Overcurrent Protection
OVC Comparator Offset Voltage
Discharge Threshold Voltage
VOUT1 Bias Current
OVC Latch Discharge Current
0V < VOUT1 ² 3.5V
0.2V ² VOUT1 ² 3.5V
VCOMP = 1V
s PWM Comparator 1
PWM Comparator Offset Voltage 0V ² VFFB1 ² 3.5V
Transient Response
VFFB1 = 0 to 3.5V
VFFB1 Bias Current
0.2V ² VFFB1 ² 3.5V
s COFF1
Off-Time
Charge Current
Discharge Current
VCOFF1 = 1.5V
VCOFF1 = 1.5V
s Power-Good Output
PWRGD Sink Current
PWRGD Upper Threshold
PWRGD Lower Threshold
PWRGD Output Low Voltage
VFB1 = 1.7V, VPWRGD = 5V
% of nominal DAC code
% of nominal DAC code
VFB1 = 1.7V, IPWRGD = 500µA
s Overvoltage Protection (OVP) Output
OVP Source Current
OVP = 1V
OVP Threshold
% of nominal DAC code
OVP Pull-up Voltage
IOVP = 1mA, VCC1 - VOVP
s VI/O Switching Regulator Error Amplifier
VFB2 Bias Current
VFB2 = 0V
COMP2 Source Current
COMP2 = 1.2V to 3.6V; VFB2 = 1V
COMP2 Sink Current
COMP2=1.2V; VFB2=1.4V;
Open Loop Gain
CCOMP2 = 0.1µF
77
0.2
-7.0
100
0.95
-7.0
1.0
0.5
5
-12
1
5
-1.0
15
30
86
0.25
0.1
800
1.06
200
0.1
1.6
550
25
4
8.5
-8.5
0.2
10
8.5
1.1
0.1
30
60
80
101
0.3
7.0
2500
1.18
300
7.0
2.3
15
12
-5
0.3
25
12
1.5
1.0
60
120
mV
V
µA
µA
V
ns
µA
µs
µA
mA
mA
%
%
V
mA
%
V
µA
µA
µA
dB
5
5 Page 
Application Information: continued
CS5132-based Dual Output
Buck Regulator Design Example
Step 1: Define Specification
Input Voltage from Òsilver boxÓ power supply
¥ 5V ±5% for conversion to output voltage
¥ 12V ±5% for NFET Gate Voltage and circuit bias
Output Voltages
¥ 2.0V @ 16A for VCC(CORE)
¥ 3.3V@ 8A for VI/O
¥ 5% Overall Voltage accuracy (load, line, temperature,
ripple)
¥ 2% DC & 5% AC Voltage Accuracy
¥ < 2% Output Ripple Voltage
¥ 15A Load Step @ 20A /µs - VCC(CORE)
¥ 7A Load Step @ 5A/µs - VI/O
Thermal Management
¥ 0 to 50û C ambient temperature range
¥ Component junction temperatures within manufactur-
erÕs specified ratings at full load & TA(MAX)
Components
¥ Low cost is top priority.
¥ Surface mount when possible
¥ Small footprint important
¥ Component Ratings determined at 80% of Maximum
Load
Step 2: Determine Output Capacitors
These components must be selected and placed carefully to
yield optimal results. Capacitors should be chosen to pro-
vide acceptable ripple on the regulator output voltage. Key
specifications for input capacitors are their ripple rating,
while ESR is important for output capacitors. For best tran-
sient response, a combination of low value/high frequency
and bulk capacitors placed close to the load will be
required.
Step 2a: For the 2V Output (VCC(CORE))
The load transients have slew rates of up to 20A /µs, while
the voltage drop during a transient must be kept to less
than 100mV. The output capacitors must hold the output
voltage within these limits since the inductor current can
not change with the required slew rate. The output capaci-
tors must therefore have a very low ESL and ESR.
The voltage transient during the load step is
( )DVOUT = DIOUT ´
ESL tTR
Dt + ESR + COUT ,
where tTR = output voltage transient response time.
The total change in output voltage is divided as follows:
ESR - 80mV
ESL - 10mV
Output Capacitor Discharge During Transient - 10mV
Maximum allowable ESR is:
ESR =
0.08V
15A
= 5.3m½.
The ESR for a 1200µF/10V Sanyo capacitor type GX is
44m½ per capacitor.
Number of Capacitors =
44
5.3
@ 8.
Total ESR =
44
8
= 5.5m½.
Output voltage deviation due to ESR:
DV = 15A ´ 5.5m½ = 82mV.
The ESL is calculated from
DI
Dt
=
20A
µs
,
ESL = DV ´ Dt = 0.01V ´ 1 ´ 10-6 = 0.5nH.
DI 20
It is estimated that a 10 ´ 12 mm Aluminum Electrolytic
capacitor has approximately 4nH of package inductance. In
this case we have eight (8) capacitors in parallel for a total
capacitor ESL:
ESL = 4nH = 0.5nH.
8
Output voltage deviation due to ESL:
DV = ESL ´ DI = 0.5nH ´ 20A = 10mV.
Dt 1µs
The change in capacitor voltage during the transient is:
DVC =
DI ´ tTR ,
COUT
where tTR is the output voltage transient response time. We
choose tTR = 6µs:
DVC =
15A ´ 6µs
8 ´ 1200µF
= 9mV.
Total change in output voltage as a result of an increase in
load current of a 15A step with a 20A/µs slew rate is:
DVOUT = ( 82mV + 10mV + 9mV ) = 101mV.
Step 2b: For the 3.3V Output (VI/O)
The VI/O load transients have slew rates of 5A/µs, while
the voltage drop during a transient must be kept to less
11
11 Page | ||
| Páginas | Total 19 Páginas | |
| PDF Descargar | [ Datasheet CS5132GDWR24.PDF ] | |
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