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PDF CS5151 Data sheet ( Hoja de datos )
| Número de pieza | CS5151 | |
| Descripción | CPU 4-Bit Nonsynchronous Buck Controller | |
| Fabricantes | Cherry Semiconductor Corporation | |
| Logotipo |  |
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CS5151
CPU 4-Bit Nonsynchronous Buck Controller
Description
Features
The CS5151 is a 4-bit nonsyn-
chronous N-Channel buck con-
troller. It is designed to provide
unprecedented transient response
for today’s demanding high-densi-
ty, high-speed logic. The regulator
operates using a proprietary control
method, which allows a 100ns
response time to load transients.
The CS5151 is designed to operate
over a 4.25-16V range (VCC) using
12V to power the IC and 5V as the
main supply for conversion.
The CS5151 is specifically designed
to power Pentium® processors with
MMX™ Technology and other high
performance core logic. It includes
the following features: on board,
4-bit DAC, short circuit protection,
1.0% output tolerance, VCC monitor,
and programmable soft start capa-
bility. The CS5151 is upwards com-
patible with the 5-bit CS5156, allow-
ing the mother board designer the
capability of using either the
CS5151 or the CS5156 with no
change in layout. The CS5151 is
available in 16 pin surface mount
and DIP packages.
Application Diagram
Switching Power Supply for core logic - Pentium® processor with MMX™ Technology
12V 5V
VID0
VID1
VID2
VID3
330pF
0.1µF
1200µF/16V x 3
AlEl
VCC1 VCC2
VGATE
VID0
VID1
VID2
VID3
CS5151
COFF
PGnd
IRL3103
2µH
2.1V to 3.5V @ 13A
MBR735
3
1,2
1200µF/16V x 5
AlEl
0.1µF
SS
COMP
0.33µF
LGnd
VFB
VFFB
3.3k
100pF
s N-Channel Design
s Excess of 1MHz Operation
s 100ns Transient Response
s 4-Bit DAC
s Upward Compatible with
5-Bit CS5155/5156 and
Adjustable CS5120/5121
s 30ns Gate Rise/Fall Times
s 1% DAC Accuracy
s 5V & 12V Operation
s Remote Sense
s Programmable Soft Start
s Lossless Short Circuit
Protection
s VCC Monitor
s Adaptive Voltage
Positioning
s V2™ Control Topology
s Current Sharing
s Overvoltage Protection
Package Options
16 Lead SO Narrow & PDIP
VID0 1
VID1
VID2
VID3
SS
NC
COFF
VFFB
VFB
COMP
LGnd
VCC1
NC
PGnd
VGATE
VCC2
V2 is a trademark of Switch Power, Inc.
Pentium is a registered trademark and MMX is a trademark of Intel Corporation.
Rev. 1/5/99
Cherry Semiconductor Corporation
2000 South County Trail, East Greenwich, RI 02818
Tel: (401)885-3600 Fax: (401)885-5786
Email: [email protected]
Web Site: www.cherry-semi.com
1 A ® Company
1 page  
Block Diagram
VCC1
SS
VID0
VID1
VID2
VID3
VFB
COMP
VFFB
LGnd
VCC1 Monitor
Comparator
-
+
3.90V
3.85V
5V
60µA
2µA
4 BIT
DAC
Error
+ Amplifier
-
Slow Feedback
PWM
Comparator
-
+
Fast Feedback
-
+
VFFB Low
1V Comparator
PWM
COMP
2.5V
SS Low
- Comparator
+
0.7V
SS High
+ Comparator
-
FAULT
RQ
SQ
FAULT
Latch
FAULT
Maximum
On-Time
Timeout
Normal
Off-Time
Timeout
Extended
Off-Time
Timeout
RQ
SQ
PWM
Latch
Off-Time
Timeout
GATE = ON
GATE = OFF
COFF
One Shot
R
SQ
Time Out
Timer
(30µs)
Edge Triggered
VCC2
VGATE
PGnd
COFF
Applications Information
Theory of Operation
V2™ Control Method
The V2™ method of control uses a ramp signal that is gen-
erated by the ESR of the output capacitors. This ramp is
proportional to the AC current through the main inductor
and is offset by the value of the DC output voltage. This
control scheme inherently compensates for variation in
either line or load conditions, since the ramp signal is gen-
erated from the output voltage itself. This control scheme
differs from traditional techniques such as voltage mode,
which generates an artificial ramp, and current mode,
which generates a ramp from inductor current.
PWM
Comparator
C
–
VGATE
Ramp
Signal
VFFB
COMP
Error
Amplifier
–
Error
Signal
E
+
Figure 1: V2™ Control Diagram
Output
Voltage
Feedback
VFB
Reference
Voltage
The V2™ control method is illustrated in Figure 1. The out-
put voltage is used to generate both the error signal and the
ramp signal. Since the ramp signal is simply the output
voltage, it is affected by any change in the output regard-
less of the origin of that change. The ramp signal also con-
tains the DC portion of the output voltage, which allows
the control circuit to drive the main switch to 0% or 100%
duty cycle as required.
A change in line voltage changes the current ramp in the
inductor, affecting the ramp signal, which causes the V2™
control scheme to compensate the duty cycle. Since the
change in inductor current modifies the ramp signal, as in
current mode control, the V2™ control scheme has the
same advantages in line transient response.
A change in load current will have an affect on the output
voltage, altering the ramp signal. A load step immediately
changes the state of the comparator output, which controls
the main switch. Load transient response is determined
only by the comparator response time and the transition
speed of the main switch. The reaction time to an output
load step has no relation to the crossover frequency of the
error signal loop, as in traditional control methods.
The error signal loop can have a low crossover frequency,
since transient response is handled by the ramp signal loop.
The main purpose of this ‘slow’ feedback loop is to provide
DC accuracy. Noise immunity is significantly improved,
since the error amplifier bandwidth can be rolled off at a low
frequency. Enhanced noise immunity improves remote sens-
5
5 Page 
Applications Information: continued
COFF timing capacitor:
COFF
=
Period × (1 - duty cycle)
4848.5
,
where:
Period =
1
switching frequency
Thermal Impedance =
TJUNCTION(MAX) - TAMBIENT
Power
A heatsink may be added to TO-220 components to reduce
their thermal impedance. A number of PC board layout
techniques such as thermal vias and additional copper foil
area can be used to improve the power handling capability
of surface mount components.
“Droop” Resistor for Adaptive Voltage Positioning
Adaptive voltage positioning is used to reduce output volt-
age excursions during abrupt changes in load current.
Regulator output voltage is offset +40mV when the regula-
tor is unloaded, and -40mV at full load. This results in
increased margin before encountering minimum and maxi-
mum transient voltage limits, allowing use of less capaci-
tance on the regulator output (see Figure 7).
To implement adaptive voltage positioning, a “droop”
resistor must be connected between the output inductor
and output capacitors and load. This is normally imple-
mented by a PC board trace of the following value:
80mV
RDROOP = IMAX
Adaptive voltage positioning can be disabled for improved
DC regulation by connecting the VFB pin directly to the load
using a separate, non-load current carrying circuit trace.
EMI Management
As a consequence of large currents being turned on and off
at high frequency, switching regulators generate noise as a
consequence of their normal operation. When designing for
compliance with EMI/EMC regulations, additional com-
ponents may be added to reduce noise emissions. These
components are not required for regulator operation and
experimental results may allow them to be eliminated. The
input filter inductor may not be required because bulk filter
and bypass capacitors, as well as other loads located on the
board will tend to reduce regulator di/dt effects on the cir-
cuit board and input power supply. Placement of the
power component to minimize routing distance will also
help to reduce emissions.
2µH 2µH
Input and Output Capacitors
These components must be selected and placed carefully to
yield optimal results. Capacitors should be chosen to pro-
vide acceptable ripple on the input supply lines and regula-
tor output voltage. Key specifications for input capacitors
are their ripple rating, while ESR is important for output
capacitors. For best transient response, a combination of
low value/high frequency and bulk capacitors placed close
to the load will be required.
Output Inductor
The inductor should be selected based on its inductance,
current capability, and DC resistance. Increasing the induc-
tor value will decrease output voltage ripple, but degrade
transient response.
Thermal Management
Thermal Considerations for Power MOSFETs and Diodes
In order to maintain good reliability, the junction tempera-
ture of the semiconductor components should be kept to a
maximum of 150°C or lower. The thermal impedance (junc-
tion to ambient) required to meet this requirement can be
calculated as follows:
33Ω
1000pF
1200µF x 3/16V +
Figure 16: Filter components
Figure 17: Input Filter
Layout Guidelines
1. Place 12V filter capacitor next to the IC and connect
capacitor ground to pin 11 (PGnd).
2. Connect pin 11 (PGnd) with a separate trace to the
ground terminals of the 5V input capacitors.
3. Place fast feedback filter capacitor next to pin 8 (VFFB)
and connect its ground terminal with a separate, wide trace
directly to pin 14 (LGnd).
4. Connect the ground terminals of the Compensation
capacitor directly to the ground of the fast feedback filter
capacitor to prevent common mode noise from effecting
the PWM comparator.
5. Place the output filter capacitor(s) as close to the load as
possible and connect the ground terminal to pin 14 (LGnd).
6. To implement adaptive voltage positioning, connect
both slow and fast feedback pins 16 (VFB) and 8 (VFFB) to
the regulator output right at the inductor terminal. Connect
inductor to the output capacitors via a trace with the fol-
lowing resistance:
11
11 Page | ||
| Páginas | Total 14 Páginas | |
| PDF Descargar | [ Datasheet CS5151.PDF ] | |
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