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PDF CS5155GN16 Data sheet ( Hoja de datos )
| Número de pieza | CS5155GN16 | |
| Descripción | CPU 5-Bit Synchronous Buck Controller | |
| Fabricantes | Cherry Semiconductor Corporation | |
| Logotipo |  |
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CS5155
CPU 5-Bit Synchronous Buck Controller
Description
Features
The CS5155 is a 5-bit synchronous
dual N-Channel buck controller. It
is designed to provide unprece-
dented transient response for
todayÕs demanding high-density,
high-speed logic. The regulator
operates using a proprietary control
method, which allows a 100ns
response time to load transients.
The CS5155 is designed to operate
over a 4.25-14V range (VCC) using
12V to power the IC and 5V as the
main supply for conversion.
The CS5155 is specifically designed
to power Pentium¨ II processors
and other high performance core
logic. It includes the following fea-
tures: on board, 5-bit DAC, short
circuit protection, 1.0% output tol-
erance, VCC monitor, and pro-
grammable soft start capability. The
CS5155 is backwards compatible
with the 4 bit CS-5150, allowing the
mother board designer the capabili-
ty of using either the CS-5150 or the
CS5155 with no change in layout.
The CS5155 is available in 16 pin
surface mount and DIP packages.
Application Diagram
Switching Power Supply for core logic - Pentium¨ II processor
12V 5V
0.1mF
VID0
VID1
VID2
VID3
VID4
330pF
VCC1
VCC2
VGATE(H)
VID0
VID1
VID2
VID3
VID4
CS5155
VGATE(L)
COFF
PGnd
0.1mF
SS
COMP
0.33mF
LGnd
VFB
VFFB
3.3k
100pF
1200mF/16V x 3
AlEl
IRL3103
2mH
1.3V to 3.5V @ 13A
IRL3103
1200mF/16V x 5
AlEl
s Dual N-Channel Design
s Excess of 1MHz Operation
s 100ns Transient Response
s 5-Bit DAC
s Backward Compatible with
4 Bit CS-5150/5151 and
Adjustable CS-5120/5121
s 30ns Gate Rise/Fall Times
s 1% DAC Accuracy
s 5V & 12V Operation
s Remote Sense
s Programmable Soft Start
s Lossless Short Circuit
Protection
s VCC Monitor
s 25ns FET Nonoverlap Time
s Adaptive Voltage
Positioning
s V2ª Control Topology
s Current Sharing
s Overvoltage Protection
Package Options
16 Lead SO Narrow & PDIP
VID0 1
VID1
VID2
VID3
SS
VID4
COFF
VFFB
VFB
COMP
LGnd
VCC1
VGATE(L)
PGnd
VGATE(H)
VCC2
V2 is a trademark of Switch Power, Inc.
Pentium is a registered trademark of Intel Corporation.
Rev. 1/22/99
Cherry Semiconductor Corporation
2000 South County Trail, East Greenwich, RI 02818
Tel: (401)885-3600 Fax: (401)885-5786
Email: [email protected]
Web Site: www.cherry-semi.com
1 A ¨ Company
1 page  
PACKAGE PIN #
16L SO Narrow & PDIP
7
8
9
10
11
12
13
14
15
16
Package Pin Description: continued
PIN SYMBOL
FUNCTION
COFF
VFFB
VCC2
VGATE(H)
PGnd
VGATE(L)
VCC1
LGnd
COMP
VFB
A capacitor from this pin to ground sets the time duration for the on
board one shot, which is used for the constant off time architecture.
Fast feedback connection to the PWM comparator. This pin is connect-
ed to the regulator output. The inner feedback loop terminates on time.
Boosted power for the high side gate driver.
High FET driver pin capable of 1.5A peak switching current. Internal
circuit prevents VGATE(H) and VGATE(L) from being in high state simul-
taneously.
High current ground for the IC. The MOSFET drivers are referenced to
this pin. Input capacitor ground and the source of lower FET should be
tied to this pin.
Low FET driver pin capable of 1.5A peak switching current.
Input power for the IC and low side gate driver.
Signal ground for the IC. All control circuits are referenced to this pin.
Error amplifier compensation pin. A capacitor to ground should be
provided externally to compensate the amplifier.
Error amplifier DC feedback input. This is the master voltage feedback
which sets the output voltage. This pin can be connected directly to the
output or a remote sense trace.
Block Diagram
VCC1
SS
VID0
VID1
VID2
VID3
VID4
VFB
COMP
VFFB
LGnd
VCC1 Monitor
Comparator
-
+
3.90V
3.85V
5V
60mA
2mA
5 BIT
DAC
Error
+ Amplifier
-
Slow Feedback
PWM
Comparator
-
+
Fast Feedback
-
+
VFFB Low
1V Comparator
PWM
COMP
2.5V
SS Low
- Comparator
+
0.7V
SS High
+ Comparator
-
Maximum
On-Time
Timeout
Normal
Off-Time
Timeout
Extended
Off-Time
Timeout
FAULT
RQ
S Q FAULT
FAULT
Latch
VCC2
VGATE(H)
PGnd
VCC1
VGATE(L)
PGnd
RQ
SQ
PWM
Latch
Off-Time
Timeout
GATE(H) = ON
GATE(H) = OFF
COFF
One Shot
R
SQ
COFF
Time Out
Timer
(30ms)
Edge Triggered
5
5 Page 
Applications Information: continued
Trace 3 = 12V Input (VCC1) and VCC2) (10V/div.)
Trace 4 = 5V Input (2V/div.)
Trace 1 = Regulator Output Voltage (1V/div.)
Trace 2 = Power Good Signal (2V/div.)
Trace 3 = VGATE(H) (10V/div.)
Math 1= VGATE(H) - 5VIN
Trace 4 = VGATE(L) (10V/div.)
Trace 2 = Inductor Switching Node (5V/div.)
Figure 16: CS5155 demonstration board during power up. Power Good
signal is activated when output voltage reaches 1.70V.
Selecting External Components
The CS5155 can be used with a wide range of external
power components to optimize the cost and performance of
a particular design. The following information can be used
as general guidelines to assist in their selection.
NFET Power Transistors
Both logic level and standard MOSFETs can be used. The
reference designs derive gate drive from the 12V supply
which is generally available in most computer systems and
utilize logic level MOSFETs. A charge pump may be easily
implemented to support 5V only systems. Multiple
MOSFETs may be paralleled to reduce losses and improve
efficiency and thermal management.
Voltage applied to the MOSFET gates depends on the
application circuit used. Both upper and lower gate driver
outputs are specified to drive to within 1.5V of ground
when in the low state and to within 2V of their respective
bias supplies when in the high state. In practice, the MOS-
FET gates will be driven rail to rail due to overshoot caused
by the capacitive load they present to the controller IC. For
the typical application where VCC1 = VCC2 = 12V and 5V is
used as the source for the regulator output current, the fol-
lowing gate drive is provided;
VGATE(H) = 12V - 5V = 7V, VGATE(L) = 12V (see Figure 17).
Figure 17: CS5155 gate drive waveforms depicting rail to rail swing.
The most important aspect of MOSFET performance is
RDSON, which effects regulator efficiency and MOSFET
thermal management requirements.
The power dissipated by the MOSFETs may be estimated
as follows;
Switching MOSFET:
Power = ILOAD2 ´ RDSON ´ duty cycle
Synchronous MOSFET:
Power = ILOAD2 ´ RDSON ´ (1 - duty cycle)
Duty Cycle =
VOUT + (ILOAD ´ RDSON OF SYNCH FET)
VIN + (ILOAD ´ RDSON OF SYNCH FET) - (ILOAD ´ RDSON OF SWITCH FET)
Off Time Capacitor (COFF)
The COFF timing capacitor sets the regulator off time:
TOFF = COFF ´ 4848.5
When the VFFB pin is less than 1V, the current charging the
COFF capacitor is reduced. The extended off time can be cal-
culated as follows:
TOFF = COFF ´ 24,242.5.
Off time will be determined by either the TOFF time, or the
time out timer, whichever is longer.
The preceding equations for duty cycle can also be used to
calculate the regulator switching frequency and select the
11
11 Page | ||
| Páginas | Total 14 Páginas | |
| PDF Descargar | [ Datasheet CS5155GN16.PDF ] | |
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