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PDF CS5166 Data sheet ( Hoja de datos )
| Número de pieza | CS5166 | |
| Descripción | 5-Bit Synchronous CPU Controller with Power-Good and Current Limit | |
| Fabricantes | Cherry Semiconductor Corporation | |
| Logotipo |  |
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CS5166
5-Bit Synchronous CPU Controller
with Power-Good and Current Limit
Description
Features
The CS5166 is a synchronous
dual NFET Buck Regulator
Controller. It is designed to pow-
er the core logic of the latest high
performance CPUs. It uses the
V2TM control method to achieve
the fastest possible transient
response and best overall regula-
tion. It incorporates many addi-
tional features required to ensure
the proper operation and protec-
tion of the CPU and power sys-
tem. The CS5166 provides the
industry’s most highly integrat-
ed solution, minimizing external
component count, total solution
size, and cost.
The CS5166 is specifically
designed to power Intel’s
Pentium® II processor and
includes the following features:
5-bit DAC with 1% tolerance,
Power-Good output, adjustable
hiccup mode over-current pro-
tection, VCC monitor, Soft Start,
adaptive voltage positioning,
over-voltage protection, remote
sense and current sharing capa-
bility.
The CS5166 will operate over a
4.15 to 14V range and is available
in a 16 lead wide body surface
mount package.
Application Diagram
5V to 2.8V @ 14.2A for 300MHz Pentium® II
5V
12V 1200µF/10V x 3
330pF
0.1µF
0.1µF
1µF
COFF
SS
COMP
VID0
VID1
VID2
VID3
VID4
VCC
GATE(H)
CS5166
ISENSE
GATE(L)
PGnd
LGnd
PWRGD VFB
1.2µH
3.0mΩ
510
0.1µF
1200µF
10V x 5
PWRGD
Pentium® II
System
3.3K
1000pF
VID4
VID3
VID2
VID1
VID0
V2 is a trademark of Switch Power, Inc.
Pentium is a registered trademark of Intel Corporation.
s V2TM Control Topology
s Dual N-Channel Design
s 125ns Controller Transient Response
s Excess of 1Mhz Operation
s 5-bit DAC with 1% Tolerance
s Power-Good Output with Internal
Delay
s Adjustable Hiccup Mode Over
Current Protection
s Complete Pentium®II System
Requires just 21 Components
s 5V and 12V Operation
s Adaptive Voltage Positioning
s Remote Sense Capability
s Current Sharing Capability
s VCC Monitor
s Overvoltage Protection (OVP)
s Programmable Soft Start
s 200ns PWM Blanking
s 65ns FET Non-Overlap
s 40ns Gate Rise and Fall Times
(3.3nF load)
Package Options
16 Lead SO WIDE
VID0 1
VID1
VID2
VID3
SS
VID4
COFF
ISENSE
VFB
COMP
LGnd
PWRGD
GATE(L)
PGnd
GATE(H)
VCC
Rev. 6/28/99
Cherry Semiconductor Corporation
2000 South County Trail, East Greenwich, RI 02818
Tel: (401)885-3600 Fax: (401)885-5786
Email: [email protected]
Web Site: www.cherry-semi.com
1 A ® Company
1 page  
Electrical Characteristics: 0˚C < TA < 70˚C; 0˚C < TJ < 125˚C; 8V < VCC < 14V; 2.0V DAC Code
(VID4 = VID3 = VID2 = VID1 =0, VID0 = 1), CGATE(H) = CGATE(L) = 3.3nF, COFF = 330pF, CSS= 0.1µF; Unless otherwise stated.
PARAMETER
TEST CONDITIONS
Accuracy (all codes except 11111) Measure VFB = COMP, (COFF = Gnd)
VID4 VID3 VID2 VID1VID0
0 0 1 00
0 0 1 01
0 0 1 10
0 0 1 11
0 1 0 00
0 1 0 01
0 1 0 10
0 1 0 11
0 1 1 00
0 1 1 01
0 1 1 10
0 1 1 11
1 1 1 11
MIN
-1.0
1.856
1.806
1.757
1.707
1.658
1.608
1.559
1.509
1.460
1.410
1.361
1.311
1.219
TYP
1.875
1.825
1.775
1.725
1.675
1.625
1.575
1.525
1.475
1.425
1.375
1.325
1.247
MAX
1.0
1.893
1.843
1.792
1.742
1.691
1.641
1.590
1.540
1.489
1.439
1.388
1.338
1.269
UNIT
%
V
V
V
V
V
V
V
V
V
V
V
V
V
Input Threshold
Input Pull-up Resistance
Input Pull-up Voltage
VID4, VID3, VID2, VID1, VID0
VID4, VID3, VID2, VID1, VID0
1.0
1.25 2.4
V
25 50 100 kΩ
4.85
5.00 5.15
V
s Power-Good Output
Low to High Delay
High to Low Delay
Output Low Voltage
Sink Current Limit
VFB = (0.8 × VDAC ) to VDAC
VFB = VDAC to (0.8 × VDAC )
VFB = 2.4V, IPWRGD = 500µA
VFB = 2.4V, PWRGD = 1V
30 65 110 µs
30 75 120 µs
0.2 0.3
V
0.5 4.0 15.0 mA
THRESHOLD ACCURACY
% of Nominal VID Code
s DAC CODE
VID4 VID3 VID2 VID1 VID0
1 0 00 0
1 0 00 1
1 0 01 0
1 0 01 1
1 0 10 0
1 0 10 1
1 0 11 0
1 0 11 1
1 1 00 0
1 1 00 1
1 1 01 0
LOWER THRESHOLD
MIN
TYP
MAX
-12 -8.5 -5
3.102
3.014
2.926
2.838
2.750
2.662
2.574
2.486
2.398
2.310
2.222
3.225
3.133
3.042
2.950
2.859
2.767
2.676
2.584
2.493
2.401
2.310
3.348
3.253
3.158
3.063
2.968
2.873
2.778
2.683
2.588
2.493
2.398
5
UPPER THRESHOLD
MIN
TYP
MAX
5 8.5 12
UNITS
%
3.701
3.596
3.491
3.386
3.281
3.176
3.071
2.966
2.861
2.756
2.651
3.824
3.716
3.607
3.499
3.390
3.282
3.173
3.065
2.956
2.848
2.739
3.948
3.836
3.724
3.612
3.500
3.388
3.276
3.164
3.052
2.940
2.828
V
V
V
V
V
V
V
V
V
V
V
5 Page 
Application Information: continued
and provided that PWRGD is low. It is also required that
the overvoltage condition be present for at least the
PWRGD delay time for the OVP signal to be activated. The
resistor values shown in Figure 15 are for VDAC = +2.8V
(DAC = 10111). The VOVP (overvoltage trip-point) can be
set using the following equation:
( )VOVP = VBEQ3 1 +
R2
R1
+5V
CS5166
10K
PWRGD
VCORE
+5V
5K
15K R1
56K R2
20K
Q2
2N3904
10K
Q1
2N3906
Q3
2N3906
10K
OVP
Figure 15: Circuit to implement a dedicated OVP output using the
CS5166.
Power-Good Circuit
The Power-Good pin (pin 13) is an open-collector signal
consistent with TTL DC specifications. It is externally
pulled -up, and is pulled low (below 0.3V) when the regu-
lator output voltage typically exceeds ± 8.5% of the nomi-
nal output voltage. Maximum output voltage deviation
before Power-Good is pulled low is ± 12%.
Trace 4 = 5V from PC Power Supply (5V/div.)
Trace1 = Regulator Output Voltage (1V/div.)
Trace 2 = Inductor Switching Node (5V/div.)
Figure 13: OVP response to an input-to-output short circuit by immedi-
ately providing 0% duty cycle, crow-barring the input voltage to
ground.
2.825V
Trace 2 - PWRGD (2V/div)
Trace 4 - VOUT (1V/div)
Figure 16: PWRGD signal becomes logic high as VOUT enters -8.5% of
lower PWRGD threshold, VOUT = +2.825V (DAC = 10111).
Trace 4 = 5V from PC Power Supply (2V/div.)
Trace 1 = Regulator Output Voltage (1V/div.)
Figure 14: OVP response to an input-to-output short circuit by pulling
the input voltage to ground.
Trace 1 PWRGD (2V/div)
Trace 4 VFB (1V/div)
Figure 17: Power-Good response to an out of regulation condition.
11
11 Page | ||
| Páginas | Total 22 Páginas | |
| PDF Descargar | [ Datasheet CS5166.PDF ] | |
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