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CS5166H 데이터시트 PDF




Cherry Semiconductor Corporation에서 제조한 전자 부품 CS5166H은 전자 산업 및 응용 분야에서
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부품번호 CS5166H 기능
기능 5-Bit Synchronous CPU Controller with Power-Good and Current Limit
제조업체 Cherry Semiconductor Corporation
로고 Cherry Semiconductor Corporation 로고


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CS5166H 데이터시트, 핀배열, 회로
CS5166H
5-Bit Synchronous CPU Controller
with Power-Good and Current Limit
Description
Features
The CS5166H is a synchronous
dual NFET Buck Regulator
Controller. It is designed to pow-
er the core logic of the latest high
performance CPUs. It uses the
V2TM control method to achieve
the fastest possible transient
response and best overall regula-
tion. It incorporates many addi-
tional features required to ensure
the proper operation and protec-
tion of the CPU and power sys-
tem. The CS5166H provides the
industry’s most highly integrat-
ed solution, minimizing external
component count, total solution
size, and cost.
The CS5166H is specifically
designed to power Intel’s
Pentium® II processor and
includes the following features:
5-bit DAC with 1% tolerance,
Power-Good output, adjustable
hiccup mode over-current pro-
tection, VCC monitor, Soft Start,
adaptive voltage positioning,
over-voltage protection, remote
sense and current sharing capa-
bility.
The CS5166H will operate over a
4.15 to 20V range using either
single or dual input voltage and
is available in a 16 lead wide
body surface mount package.
Application Diagram
5V to 2.8V @ 14.2A for 300MHz Pentium® II
5V
12V 1200µF/10V x 3
330pF
0.1µF
0.1µF
1µF
COFF
SS
COMP
VID0
VID1
VID2
VID3
VID4
VCC
GATE(H)
CS5166H
ISENSE
GATE(L)
PGnd
LGnd
PWRGD VFB
1.2µH
3.0m
510
0.1µF
1200µF
10V x 5
PWRGD
Pentium® II
System
3.3K
1000pF
VID4
VID3
VID2
VID1
VID0
V2 is a trademark of Switch Power, Inc.
Pentium is a registered trademark of Intel Corporation.
s V2TM Control Topology
s Dual N-Channel Design
s 125ns Controller Transient Response
s Excess of 1Mhz Operation
s 5-bit DAC with 1% Tolerance
s Power-Good Output with Internal
Delay
s Adjustable Hiccup Mode Over
Current Protection
s Complete Pentium®II System
Requires just 21 Components
s 5V and 12V Operation using either
Dual or Single Supplies
s Adaptive Voltage Positioning
s Remote Sense Capability
s Current Sharing Capability
s VCC Monitor
s Overvoltage Protection (OVP)
s Programmable Soft Start
s 200ns PWM Blanking
s 65ns FET Non-Overlap
s 40ns Gate Rise and Fall Times
(3.3nF load)
Package Options
16 Lead SO WIDE
VID0 1
VID1
VID2
VID3
SS
VID4
COFF
ISENSE
VFB
COMP
LGnd
PWRGD
GATE(L)
PGnd
GATE(H)
VCC
Rev. 6/28/99
Cherry Semiconductor Corporation
2000 South County Trail, East Greenwich, RI 02818
Tel: (401)885-3600 Fax: (401)885-5786
Web Site: www.cherry-semi.com
1 A ® Company




CS5166H pdf, 반도체, 판매, 대치품
Electrical Characteristics: 0˚C < TA < 70˚C; 0˚C < TJ < 125˚C; 8V < VCC < 20V; 2.0V DAC Code (VID4 = VID3 = VID2 =
VID1 =0, VID0 = 1), CGATE(H) = CGATE(L) = 3.3nF, COFF = 330pF, CSS= 0.1µF; Unless otherwise stated.
PARAMETER
s Fault Protection continued
SS Comp Clamp Voltage
VFB Low Comparator
TEST CONDITIONS
VFB = 2.7V, VSS = 0V
Increase VFB till normal off-time
MIN
0.50
0.9
TYP
0.95
1.0
MAX
UNIT
1.10 V
1.1 V
s PWM Comparator
Transient Response
Minimum Pulse Width
(Blanking Time)
s COFF
Normal Off-Time
Extended Off-Time
VFB = 1.2V to 5V 500ns after GATE(H)
(after Blanking time) to
GATE(H) = (VCC – 1V)
to 1V, 8V < VCC < 14V
Drive VFB 1.2V to 5V upon GATE(H)
rising edge (> VCC – 1V), measure
GATE(H) pulse width,
8V < VCC < 14V
100
VFB = 2.7V
VSS = VFB = 0V
1.0
5.0
115 175
ns
200 300
ns
1.6 2.3
8.0 12.0
µs
µs
s Time-Out Timer
Time-Out Time
Fault Duty Cycle
VFB = 2.7V, Measure GATE(H) 10 30 50 µs
Pulse Width
VFB = 0V
30 50 70 %
s Voltage Identification DAC
Accuracy (all codes except 11111)
VID4 VID3 VID2 VID1VID0
1 0 0 00
1 0 0 01
1 0 0 10
1 0 0 11
1 0 1 00
1 0 1 01
1 0 1 10
1 0 1 11
1 1 0 00
1 1 0 01
1 1 0 10
1 1 0 11
1 1 1 00
1 1 1 01
1 1 1 10
0 0 0 00
0 0 0 01
0 0 0 10
0 0 0 11
Measure VFB = COMP, (COFF = Gnd)
25˚C TJ 125˚C, VCC = 12V
4
-1.0
3.489
3.390
3.291
3.192
3.093
2.994
2.895
2.796
2.697
2.598
2.499
2.400
2.301
2.202
2.103
2.054
2.004
1.955
1.905
3.525
3.425
3.325
3.225
3.125
3.025
2.925
2.825
2.725
2.625
2.525
2.425
2.325
2.225
2.125
2.075
2.025
1.975
1.925
1.0
3.560
3.459
3.358
3.257
3.156
3.055
2.954
2.853
2.752
2.651
2.550
2.449
2.348
2.247
2.146
2.095
2.045
1.994
1.944
%
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V

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CS5166H 전자부품, 판매, 대치품
Application Information
Theory Of Operation
V2TM Control Method
The V2TM method of control uses a ramp signal that is gen-
erated by the ESR of the output capacitors. This ramp is
proportional to the AC current through the main inductor
and is offset by the value of the DC output voltage. This
control scheme inherently compensates for variation in
either line or load conditions, since the ramp signal is gen-
erated from the output voltage itself. This control scheme
differs from traditional techniques such as voltage mode,
which generates an artificial ramp, and current mode,
which generates a ramp from inductor current.
PWM
Comparator
C
GATE(H)
GATE(L)
of the CS5166H single pole feedback loop and demon-
strates the overall stability of the CS5166H-based regulator.
.1µF
10K
Open Loop
49.63
BW
62.3 KHz
Phase margin
81.9
Figure 2: Feedback loop Bode Plot.
COMP
Ramp Signal
Error
Amplifier
Error
Signal
E
+
VFB
Reference
Voltage
Figure 1: V2TM Control Diagram.
The V2TM control method is illustrated in Figure 1. The out-
put voltage is used to generate both the error signal and
the ramp signal. Since the ramp signal is simply the output
voltage, it is affected by any change in the output regard-
less of the origin of that change. The ramp signal also con-
tains the DC portion of the output voltage, which allows
the control circuit to drive the main switch to 0% or 100%
duty cycle as required.
A change in line voltage changes the current ramp in the
inductor, affecting the ramp signal, which causes the V2TM
control scheme to compensate the duty cycle. Since the
change in inductor current modifies the ramp signal, as in
current mode control, the V2TM control scheme has the same
advantages in line transient response.
A change in load current will have an affect on the output
voltage, altering the ramp signal. A load step immediately
changes the state of the comparator output, which controls
the main switch. Load transient response is determined
only by the comparator response time and the transition
speed of the main switch. The reaction time to an output
load step has no relation to the crossover frequency of the
error signal loop, as in traditional control methods.
The error signal loop can have a low crossover frequency,
since transient response is handled by the ramp signal
loop. The main purpose of this ‘slow’ feedback loop is to
provide DC accuracy. Noise immunity is significantly
improved, since the error amplifier bandwidth can be
rolled off at a low frequency. Enhanced noise immunity
improves remote sensing of the output voltage, since the
noise associated with long feedback traces can be effective-
ly filtered.
The Bode plot in Figure 2 shows the gain and phase margin
Line and load regulation are drastically improved because
there are two independent voltage loops. A voltage mode
controller relies on a change in the error signal to compen-
sate for a deviation in either line or load voltage. This
change in the error signal causes the output voltage to
change corresponding to the gain of the error amplifier,
which is normally specified as line and load regulation.
A current mode controller maintains fixed error signal
under deviation in the line voltage, since the slope of the
ramp signal changes, but still relies on a change in the error
signal for a deviation in load. The V2TM method of control
maintains a fixed error signal for both line and load varia-
tion, since the ramp signal is affected by both line and load.
Constant Off-Time
To maximize transient response, the CS5166H uses a
Constant Off-Time method to control the rate of output
pulses. During normal operation, the Off-Time of the high
side switch is terminated after a fixed period, set by the
COFF capacitor. To maintain regulation, the V2TM Control
Loop varies switch On-Time. The PWM comparator moni-
tors the output voltage ramp, and terminates the switch
On-Time.
Constant Off-Time provides a number of advantages.
Switch duty Cycle can be adjusted from 0 to 100% on a
pulse-by pulse basis when responding to transient condi-
tions. Both 0% and 100% Duty Cycle operation can be
maintained for extended periods of time in response to
Load or Line transients. PWM Slope Compensation to
avoid sub-harmonic oscillations at high duty cycles is
avoided.
Switch On-Time is limited by an internal 30µs (typical)
timer, minimizing stress to the Power Components
Programmable Output
The CS-5166H is designed to provide two methods for pro-
gramming the output voltage of the power supply. A five
bit on board digital to analog converter (DAC) is used to
program the output voltage within two different ranges.
7

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