PDF CS52845ED8 Data sheet ( Hoja de datos )

Número de pieza	CS52845ED8
Descripción	Current Mode PWM Control Circuit with 50% Max Duty Cycle
Fabricantes	Cherry Semiconductor Corporation
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No Preview Available ! CS52845 Current Mode PWM Control Circuit with 50% Max Duty Cycle Description The CS52845 provides all the nec- essary features to implement off- line fixed frequency current-mode control with a minimum number of external components. The CS52845 incorporates a new precision temperature-controlled oscillator to minimize variations in frequency. An internal toggle flip- flop, which blanks the output every other clock cycle, limits the duty-cycle range to less than 50%. An undervoltage lockout ensures that VREF is stabilized before the output stage is enabled. In the CS52845 turn on is at 8.4V and turn off at 7.6V. Other features include low start-up current, pulse-by-pulse current lim- iting, and a high-current totem pole output for driving capacitive loads, such as gate of a power MOSFET. The output is low in the off state, consistent with N-channel devices. Absolute Maximum Ratings Supply Voltage (ICC<30mA) ..........................................................Self Limiting Supply Voltage (Low Impedance Source)...................................................30V Output Current ...............................................................................................±1A Output Energy (Capacitive Load) .................................................................5µJ Analog Inputs (VFB, VSENSE)...........................................................-0.3V to 5.5V Error Amp Output Sink Current...............................................................10mA Lead Temperature Soldering Reflow (SMD styles only) ...........60 sec. max above 183°C, 230°C peak Block Diagram VCC VCC Undervoltage Lock-out 34V Gnd VFB COMP OSC Sense 8.4V/7.6V Set/ 5.0 Volt Reset Reference Error Amplifier - + 2.50V Oscillator VREF R Undervoltage Lockout R Toggle Flip-Flop 2R R S R 1V Current PWM Sensing Latch Comparator NOR Internal Bias VCC Pwr VREF VOUT Pwr Gnd Features s Optimized for Off-line Control s Temperature Compensated Oscillator s 50% Maximum Duty-cycle Clamp s VREF Stabilized before Output Stage is Enabled s Low Start-up Current s Pulse-by-pulse Current Limiting s Improved Undervoltage Lockout s Double Pulse Suppression s 1% Trimmed Bandgap Reference s High Current Totem Pole Output Package Options 8L SO Narrow COMP 1 VFB 2 Sense 3 OSC 4 8 VREF 7 VCC 6 VOUT 5 Gnd 14L SO Narrow COMP 1 NC 2 VFB 3 NC 4 Sense 5 NC 6 OSC 7 14 VREF 13 NC 12 VCC 11 VCC Pwr 10 VOUT 9 Gnd 8 Pwr Gnd Rev. 3/4/99 Cherry Semiconductor Corporation 2000 South County Trail, East Greenwich, RI 02818 Tel: (401)885-3600 Fax: (401)885-5786 Email: [email protected] Web Site: www.cherry-semi.com 1 A Company ® 1 page VOSC OSC RESET Toggle F/F Output EA Output Switch Current VCC IO VO Figure 2: Timing Diagram Vupper Vlower ton tc td ton=tc toff=tc+2td Figure 3: Duty Cycle parameters. Circuit Description:: continued Setting the Oscillator The times Tc and Td can be determined as follows: ( )tc = RTCT ln VREF - Vlower VREF - Vupper ( )td = RTCT ln VREF - IdRT - Vlower VREF - IdRT - Vupper Substituting in typical values for the parameters in the above formulas: VREF = 5.0V, Vupper = 2.7V, Vlower = 1.0V, Id = 8.3mA, then tc ≈ 0.5534RTCT ( )td = RTCT ln 2.3 - 0.0083 RT 4.0 - 0.0083 RT For better accuracy RT should be ≥10kΩ. Grounding toff High peak currents associated with capacitive loads neces- sitate careful grounding techniques. Timing and bypass capacitors should be connected close to Gnd in a single point ground. The transistor and 5kΩ potentiometer are used to sample the oscillator waveform and apply an adjustable ramp to Sense. 5 5 Page

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