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CS5336-KP 데이터시트 PDF




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부품번호 CS5336-KP 기능
기능 16-Bit/ Stereo A/D Converters for Digital Audio
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CS5336-KP 데이터시트, 핀배열, 회로
Semiconductor Corporation
CS5336 CS5338 CS5339
16-Bit, Stereo A/D Converters for Digital Audio
Features
Complete CMOS Stereo A/D System
Delta-Sigma A/D Converters
Digital Anti-Alias Filtering
S/H Circuitry and Voltage Reference
Adjustable System Sampling Rates
including 32kHz, 44.1 kHz & 48kHz
Low Noise and Distortion
>90 dB S/(N+D)
Internal 64X Oversampling
Linear Phase Digital Anti-Alias Filtering
0.01dB Passband Ripple
80dB Stopband Rejection
Low Power Dissipation: 400 mW
Power-Down Mode for Portable
Applications
Evaluation Board Available
General Description
The CS5336, CS5338 & CS5339 are complete analog-
to-digital converters for stereo digital audio systems.
They perform sampling, analog-to-digital conversion and
anti-aliasing filtering, generating 16-bit values for both
left and right inputs in serial form. The output word rate
can be up to 50 kHz per channel.
The ADCs use delta-sigma modulation with 64X over-
sampling, followed by digital filtering and decimation,
which removes the need for an external anti-alias filter.
The CS5336 & CS5338 have an SCLK which clocks out
data on rising edges. The CS5339 has an SCLK which
clocks out data on falling edges.
The CS5336 has a filter passband of dc to 22kHz. The
CS5338 & CS5339 have a filter passband of dc to 24
kHz. The filters have linear phase, 0.01 dB passband
ripple, and >80 dB stopband rejection.
The ADC’s are housed in a 0.6" wide 28-pin plastic DIP,
and also in a 0.3" wide 28-pin SOIC surface mount
package. Extended temperature range versions of the
CS5336 are also available.
ORDERING INFORMATION: See Page 3-59
28
VREF
ICLKA APD ACAL
23 6
7
Voltage Reference
A IN L
ZEROL
2
3
S/H
AIN R
ZEROR
27
26
AGND 1
S /H
LP Filter
Com parator
DAC
LP Filter
Com parator
DAC
O C LKD ICLKD FSYN C SCLK L/R
21 20
1 7 15 14
S erial O utput Interface
16
12 S D A T A
13
CMODE
SMODE
Digital Decimation
Filter
11
TST
Digital Decim ation
Filter
C a lib ra tio n
Microcontroller
8
C a lib ra tio n
NC
SRAM
22
NC
45
VA+ VA-
25 24
VL+ LGND
9 10
DCAL DPD
18 19
VD+ DGND
Crystal Semiconductor Corporation
P.O. Box 17847, Austin, TX 78760
(512) 445-7222 FAX: (512) 445-7581
AUG ’93
DS23F1
3-39




CS5336-KP pdf, 반도체, 판매, 대치품
CS5336, CS5338, CS5339
SWITCHING CHARACTERISTICS
(TA = 25 °C; VA+, VL+, VD+ = 5V ± 5%; VA- = -5V ± 5%; Inputs: Logic 0 = 0V, Logic 1 = VD+; CL = 20 pF)
Parameter
Symbol Min Typ Max Unit
ICLKD Period (CMODE low)
(Note 6)
ICLKD Low (CMODE low)
ICLKD High (CMODE low)
ICLKD rising to OCLKD rising (CMODE low)
ICLKD Period (CMODE high)
ICLKD Low (CMODE high)
ICLKD High (CMODE high)
ICLKD rising or falling to OCLKD rising (CMODE high, Note 4)
ICLKD rising to L/R edge (CMODE low, MASTER mode)
ICLKD rising to FSYNC edge (CMODE low, MASTER mode)
ICLKD rising to SCLK edge (CMODE low, MASTER mode)
ICLKD falling to L/R edge (CMODE high, MASTER mode)
ICLKD falling to FSYNC edge (CMODE high, MASTER mode)
ICLKD falling to SCLK edge (CMODE high, MASTER mode)
SCLK rising to SDATA valid (MASTER mode, Note 5)
SCLK duty cycle (MASTER mode)
t clkw1
t clkl1
t clkh1
t io1
t clkw2
t clkl2
t clkh2
t io2
t ilr1
t ifs1
t isclk1
t ilr2
t ifs2
t isclk2
t sdo
78
31
31
5
52
20
20
5
5
5
5
5
5
5
0
40
- 3906
--
--
- 40
- 2604
--
--
- 45
- 50
- 50
- 50
- 50
- 50
- 50
- 50
50 60
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
%
SCLK rising to L/R (MASTER mode, Note 5)
t mslr
-20
SCLK rising to FSYNC (MASTER mode, Note 5)
t msfs
-20
SCLK Period (SLAVE mode)
t sclkw
155
SCLK Pulse Width Low (SLAVE mode)
t sclkl
60
SCLK Pulse Width High (SLAVE mode)
SCLK rising to SDATA valid (SLAVE mode, Note 5)
t sclkh
t dss
60
-
L/R edge to MSB valid (SLAVE mode)
t lrdss
-
Falling SCLK to L/R edge delay (SLAVE mode, Note 5)
t slr1
30
L/R edge to falling SCLK setup time (SLAVE mode, Note 5)
t slr2
30
Falling SCLK to rising FSYNC delay (SLAVE mode, Note 5)
t sfs1
30
Rising FSYNC to falling SCLK setup time (SLAVE mode, Note 5)
t sfs2
30
DPD pulse width
t pdw 2 x tclkw
DPD rising to DCAL rising
t pcr -
DPD falling to DCAL falling (OWR = Output Word Rate)
t pcf -
Notes: 4. ICLKD rising or falling depends on DPD to L/R timing (see Figure 2).
5. SCLK is shown for CS5336, CS5338. SCLK is inverted for CS5339.
6. Specifies minimum output word rate (OWR) of 1 kHz.
-
-
-
-
-
-
-
-
-
-
-
-
-
4096
20 ns
20 ns
- ns
- ns
- ns
50 ns
50 ns
- ns
- ns
- ns
- ns
- ns
50 ns
- 1/OWR
3-42
DS23F1

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CS5336-KP 전자부품, 판매, 대치품
CS5336, CS5338, CS5339
GENERAL DESCRIPTION
The CS5336, CS5338, and CS5339 are 16-bit, 2-
channel A/D converters designed specifically for
stereo digital audio applications. The devices use
two one-bit delta-sigma modulators which simul-
taneously sample the analog input signals at a 64
X sampling rate. The resulting serial bit streams
are digitally filtered, yielding pairs of 16-bit val-
ues. This technique yields nearly ideal conversion
performance independent of input frequency and
amplitude. The converters do not require difficult-
to-design or expensive anti-alias filters, and do not
require external sample-and-hold amplifiers or a
voltage reference.
An on-chip voltage reference provides for an in-
put signal range of ± 3.68 volts. Any zero offset is
internally calibrated out during a power-up self-
calibration cycle. Output data is available in serial
form, coded as 2’s complement 16-bit numbers.
Typical power consumption of only 400 mW can
be further reduced by use of the power-down
mode.
For more information on delta-sigma modulation
and the particular implementation inside these
ADCs, see the references at the end of this data
sheet.
L/R CMODE
(kHz)
32 low
32 high
44.1 low
44.1 high
48 low
48 high
ICLKD
(MHz)
OCLKD/
ICLKA
(MHz)
SCLK
(MHz)
8.192 4.096 2.048
12.288 4.096 2.048
11.2896 5.6448 2.8224
16.9344 5.6448 2.8224
12.288 6.144 3.072
18.432 6.144 3.072
Table 1. Common Clock Frequencies
DS23F1
SYSTEM DESIGN
Very few external components are required to sup-
port the ADC. Normal power supply decoupling
components, voltage reference bypass capacitors
and a single resistor and capacitor on each input
for anti-aliasing are all that’s required, as shown
in Figure 1.
Master Clock Input
The master input clock (ICLKD) into the ADC
runs the digital filter, and is used to generate the
modulator sampling clock. ICLKD frequency is
determined by the desired Output Word Rate
(OWR) and the setting of the CMODE pin.
CMODE high will set the required ICLKD fre-
quency to 384 X OWR, while CMODE low will
set the required ICLKD frequency to 256 X
OWR. Table 1 shows some common clock fre-
quencies. The digital output clock (OCLKD) is
always equal to 128 X OWR, which is always
2 X the input sample rate. OCLKD should be
connected to ICLKA, which controls the input
sample rate.
The phase alignment between ICLKD and
OCLKD is determined as follows: when CMODE is
ICLKD
Input
01234567
DPD
Inp_ut
L/ R
Input
*
1 **
OCLKD
Ou_tput
L/ R
Input
1
2
***
OCLKD 2
Output
* DPD low is recognized on the next ICLKD rising edge (#0)
** L/R rising before ICLKD rising #2 causes OCLKD -1
*** L/R rising after ICLKD rising #2 causes OCLKD - 2
Figure 2. ICLKD to OCLKD Timing with CMODE
high (384 X OWR)
3-45

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관련 데이터시트

부품번호상세설명 및 기능제조사
CS5336-KP

16-Bit/ Stereo A/D Converters for Digital Audio

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