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CS5360 데이터시트 PDF




Cirrus Logic에서 제조한 전자 부품 CS5360은 전자 산업 및 응용 분야에서
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부품번호 CS5360 기능
기능 24-Bit Stereo A/D Converter for Digital Audio
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CS5360 데이터시트, 핀배열, 회로
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CDB5334/35/60
Evaluation Board for CS5334/CS5335/CS5360
Features
l Demonstrates recommended layout and
grounding arrangements
l CS8402A Generates AES/EBU, S/PDIF, &
EIAJ-340 Compatible Digital Audio
l Buffered Serial Output Interface
l Digital and Analog Patch Areas
l On-board or externally supplied system
timing
I
Description
The CDB5334/35/60 evaluation board is an excellent
means for quickly evaluating the CS5334, CS5335, or
CS5360 stereo A/D converters. Evaluation requires a
digital signal processor, a low distortion analog signal
source and a power supply. Analog inputs are provided
via XLR connectors for both channels.
Also included is a CS8402A digital audio interface trans-
mitter which generates AES/EBU, S/PDIF, and EIAJ-340
compatible audio data. The digital audio data is available
via RCA phono, and optical connectors.
The evaluation board may also be configured to accept
external timing signals for operation in a user application
during system development.
ORDERING INFO
CDB5334/35/60
Preliminary Product Information
Cirrus Logic, Inc.
Crystal Semiconductor Products Division
P.O. Box 17847, Austin, Texas 78760
(512) 445 7222 FAX: (512) 445 7581
http://www.crystal.com
This document contains information for a new product.
Cirrus Logic reserves the right to modify this product without notice.
Copyright © Cirrus Logic, Inc. 1997
(All Rights Reserved)
OCT ‘97
DS194DB3
1




CS5360 pdf, 반도체, 판매, 대치품
CDB5334/35/60
but inverting the SCLK so that data is valid on the
falling edge of SCLK will make the Format 0 inter-
face lines match the Format 1 interface lines on the
CS8402A. The PLD configures the CS8402A to
Format 1 and performs SCLK inversion automati-
cally when the DIF1, DIF0 switches on SW1 are set
to 00.
Digital Interface Format 1 on the CS5334, CS5335,
and CS5360 has valid data on the falling edge of
SCLK. This interface format matches Format 1 on
the CS8402A, so no modification is performed on
the digital interface lines. The PLD configures the
CS8402A to FORMAT 1 and passes the interface
lines from the CS5334, CS5335, or CS5360
through to the CS8402A unchanged when the
DIF1, DIF0 switches are set to 01.
Digital Interface Format 2 is the I2S compatible
mode. It matches Format 4 on the transmitter. The
PLD configures the CS8402A to Format 4 and
passes the interface lines from the CS5334,
CS5335, or CS5360 through to the CS8402A un-
changed when the DIF1, DIF0 switches are set to
10.
CS8402A MCLK Generation
When the CDB5334/35/60 is set up for SLAVE
mode, the crystal oscillator (U5) can be 256x,
384x, or 512x Fs. The CS8402A requires a master
clock frequency of 128x Fs to operate. The PLD
can be configured to divide MCLK_5335 (the os-
cillator output) by 2, 3, or 4 to generate
MCLK_8402, thus accommodating the various
possible frequencies of the oscillator. The switches
on SW1 labeled MCLK_S1 and MCLK_S0 select
the degree of clock division as defined in Table 3.
Decoding PSL bits / Driving LEDs
The PLD decodes and displays the Peak Signal
Level bits for both High Resolution and Bargraph
modes (for detailed information on the PSL bits,
see the CS5334/CS5335 and CS5360 datasheets).
When the TMODE1 and TMODE2 jumpers, de-
fined in Table 2, are set to BARGRAPH, the PLD
decodes the PSL bits and drives bargraph LEDs for
the left and right channels. When the TMODE1 and
TMODE2 jumpers are set to HI RES (High Reso-
lution mode), the PLD drives the 7 segment dis-
plays for left and right channels.
The PLD also provides a Peak Update (PU) signal,
which adjusts the rate at which the PSL bits are up-
dated. Four settings provide update rates ranging
from 42 ms to 2.7 s (for a 48 kHz sample rate). The
switches on SW1 labeled PU_S1 and PU_S0 select
the PU frequency as shown in Table 3.
GROUNDING AND POWER SUPPLY
DECOUPLING
The CS5334, CS5335, and CS5360 require careful
attention to power supply and grounding arrange-
ments to optimize performance. Figure 4 shows the
recommended power arrangements. The CS5334,
CS5335, or CS5360 is positioned over the analog
ground plane, near the digital/analog ground plane
split, to minimize the distance that the clocks trav-
el. The series resistors are present on the clock and
data lines to reduce the effects of transient currents
when driving a capacitive load in MASTER mode,
and to reduce clock overshoot when applying ex-
ternal clocks to the ADC in SLAVE mode.
This layout technique is used to minimize digital
noise and to insure proper power supply match-
ing/sequencing. The decoupling capacitors are lo-
cated as close to the ADC as possible. Extensive
use of ground plane fill on both the analog and dig-
ital sections of the evaluation board yield large re-
ductions in radiated noise effects.
4 DS194DB3

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CS5360 전자부품, 판매, 대치품
CDB5334/35/60
Switch # 0 = closed, 1 = open
Comment
6
PRO = 1
Pofessional Mode (C0 = 1)
8
CRE
Local Sample Address Counter and Reliability Flags
0 Disabled
1 Internally Generated
7, 4
C6, C7
C6, C7 - Sample Frequency
0 0 00 - Not Indicated - Default to 48 kHz
0 1 01 - 48 kHz
1 0 10 - 44.1 kHz
1 1 11 - 32 kHz
5 C1 C1 - Audio
1 0 - Normal Audio
0 1 - Non-Audio
3 C9 C8, C9, C10, C11 - Channel Mode (1 of 4 bits)
1 0000 - Not Indicated - Default to 2-channel
0 0100 - Stereophonic
1, 2
EM1, EM0
C2, C3, C4 - Emphasis (2 of 3 bits)
1 1 000 - Not Indicated - Default to none
1 0 100 - No emphasis
0 1 110 - 50/15 µs
0 0 111 - CCITTJ.17
Table 5. CS8402A Switch Definitions - Professional Mode
DS194DB3
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관련 데이터시트

부품번호상세설명 및 기능제조사
CS5360

24-Bit Stereo A/D Converter for Digital Audio

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Cirrus Logic
CS5360

(CS5334 - CS5360) Evaluation Board

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