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PDF CS5361 Data sheet ( Hoja de datos )
| Número de pieza | CS5361 | |
| Descripción | Multi-Bit Audio A/D Converter | |
| Fabricantes | Cirrus Logic | |
| Logotipo |  |
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CS5361
114 dB, 192 kHz, Multi-Bit Audio A/D Converter
Features
General Description
z Advanced Multi-bit Delta-sigma Architecture
z 24-bit Conversion
z 114 dB Dynamic Range
The CS5361 is a complete analog-to-digital converter for
digital audio systems. It performs sampling, analog-to-
digital conversion, and anti-alias filtering. The CS5361
generates 24-bit values for both left and right inputs in
serial form at sample rates up to 192 kHz per channel.
z -105 dB THD+N
z System Sampling Rates up to 192 kHz
z 135 mW Power Consumption
z High-pass Filter and DC Offset Calibration
z Supports Logic Levels Between 5 and 2.5 V
z Differential Analog Architecture
The CS5361 uses a 5th-order, multi-bit, delta-sigma
modulator followed by digital filtering and decimation.
This removes the need for an external anti-alias filter.
The ADC uses a differential architecture which provides
excellent noise rejection.
The CS5361 is ideal for audio systems requiring wide dy-
namic range, negligible distortion, and low noise. These
applications include A/V receivers, DVD-R, CD-R, digital
mixing consoles, and effects processors.
z Overflow Detection
z Pin-compatible with the CS5381
ORDERING INFORMATION
CS5361-KSZ -10° to 70°C 24-pin SOIC Lead Free
CS5361-KZZ -10° to 70°C 24-pin TSSOP Lead Free
CS5361-DZZ -40° to 85°C 24-pin TSSOP Lead Free
CDB5361
Evaluation Board
VQ REFGND
OVFL VL SCLK LRCK SDOUT MCLK
FILT+
Voltage Reference
AINL-
AINL+
+
-
S/H
AINR-
AINR+
+
-
S/H
LP Filter
DAC
LP Filter
DAC
Serial Output Interface
Digital
∆Σ Decimation
Filter
High
Pass
Filter
Digital
∆Σ Decimation
Filter
High
Pass
Filter
RST
I2S/LJ
M/S
HPF
MDIV
MODE0
MODE1
http://www.cirrus.com
Copyright © Cirrus Logic, Inc. 2005
(All Rights Reserved)
FEB ‘05
DS467F2
1
1 page  
CS5361
ANALOG CHARACTERISTICS (CS5361-KSZ/KZZ)
Test conditions (unless otherwise specified): Input test signal is a 1 kHz sine wave; measurement bandwidth is
10 Hz to 20 kHz.
Parameter
Single Speed Mode
Fs = 48 kHz
Dynamic Range
A-weighted
unweighted
Total Harmonic Distortion + Noise
(Note 4)
-1 dB
-20 dB
-60 dB
Double Speed Mode
Fs = 96 kHz
Dynamic Range
A-weighted
unweighted
40 kHz bandwidth unweighted
Total Harmonic Distortion + Noise
40 kHz bandwidth
(Note 4)
-1 dB
-20 dB
-60 dB
-1 dB
Quad Speed Mode
Fs = 192 kHz
Dynamic Range
A-weighted
unweighted
40 kHz bandwidth unweighted
Total Harmonic Distortion + Noise
40 kHz bandwidth
(Note 4)
-1 dB
-20 dB
-60 dB
-1 dB
Dynamic Performance for All Modes
Interchannel Isolation
DC Accuracy
Interchannel Gain Mismatch
Gain Error
Gain Drift
Offset Error
HPF enabled
HPF disabled
Analog Input Characteristics
Full-scale Input Voltage
Input Impedance (Differential)
(Note 5)
Common Mode Rejection Ratio
Symbol
THD+N
THD+N
THD+N
CMRR
Min
108
105
-
-
-
108
105
-
-
-
-
-
108
105
-
-
-
-
-
-
-
-2
-100
-
-
1.10*VA
7.5
-
Typ
114
111
-105
-91
-51
114
111
108
-105
-91
-51
-102
114
111
108
-105
-91
-51
-102
110
0.1
-
-
-
-
1.13*VA
-
82
Max
Unit
- dB
- dB
-99 dB
- dB
- dB
- dB
- dB
- dB
-99 dB
- dB
- dB
- dB
- dB
- dB
- dB
-99 dB
- dB
- dB
- dB
- dB
- dB
2%
100 ppm/°C
0 LSB
100 LSB
1.15*VA
-
-
Vpp
kΩ
dB
Notes: 4. Referred to the typical full-scale input voltage.
5. Measured between AIN+ and AIN-
DS467F2
5
5 Page 
CS5361
SWITCHING CHARACTERISTICS - SERIAL AUDIO PORT
Logic “0” = GND = 0 V; Logic “1” = VL, CL = 20 pF
Parameter
Symbol
Output Sample Rate
Single Speed Mode
Double Speed Mode
Quad Speed Mode
Fs
Fs
Fs
OVFL to LRCK edge setup time
OVFL to LRCK edge hold time
tsetup
thold
OVFL time-out on overrange condition
Fs = 44.1, 88.2, 176.4 kHz
Fs = 48, 96, 192 kHz
MCLK Specifications
MCLK Period
MCLK Pulse Duty Cycle
tclkw
Master Mode
SCLK falling to LRCK
SCLK falling to SDOUT valid
SCLK Duty Cycle
tmslr
tsdo
Slave Mode
Single Speed
Output Sample Rate
Fs
LRCK Duty Cycle
SCLK Period
SCLK Duty Cycle
tsclkw
SCLK falling to SDOUT valid
SCLK falling to LRCK edge
Double Speed
tdss
tslrd
Output Sample Rate
Fs
LRCK Duty Cycle
SCLK Period
SCLK Duty Cycle
tsclkw
SCLK falling to SDOUT valid
SCLK falling to LRCK edge
Quad Speed
tdss
tslrd
Output Sample Rate
Fs
LRCK Duty Cycle
SCLK Period
SCLK Duty Cycle
tsclkw
SCLK falling to SDOUT valid
SCLK falling to LRCK edge
tdss
tslrd
Min
2
50
100
16/fsclk
1/fsclk
-
-
38
40
-20
0
-
2
40
153
45
-
-20
50
40
153
45
-
-20
100
40
77
45
-
-8
Typ
-
-
-
-
-
740
680
-
50
-
-
50
-
50
-
50
-
-
-
50
-
50
-
-
-
50
-
50
-
-
Max
51
102
204
-
-
-
-
Unit
kHz
kHz
kHz
s
s
ms
ms
1953
60
20
32
-
ns
%
ns
ns
%
51 kHz
60 %
- ns
55 %
32 ns
20 ns
102 kHz
60 %
- ns
55 %
32 ns
20 ns
204 kHz
60 %
- ns
55 %
32 ns
3 ns
DS467F2
11
11 Page | ||
| Páginas | Total 23 Páginas | |
| PDF Descargar | [ Datasheet CS5361.PDF ] | |
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