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PDF CS5534 Data sheet ( Hoja de datos )
| Número de pieza | CS5534 | |
| Descripción | 16-bit and 24-bit ADC | |
| Fabricantes | Cirrus Logic | |
| Logotipo |  |
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CS5531/32/33/34
16-Bit and 24-Bit ADCs with Ultra Low Noise PGIA
Features
Chopper Stabilized PGIA (Programmable
Gain Instrumentation Amplifier, 1x to 64x)
6 nV/√Hz @ 0.1 Hz (No 1/f noise) at 64x
500 pA Input Current with Gains >1
Delta-Sigma Analog-to-Digital Converter
Linearity Error: 0.0007% FS
Noise Free Resolution: Up to 23 bits
Two or Four Channel Differential MUX
Scalable Input Span via Calibration
±5 mV to differential ±2.5V
Scalable VREF Input: Up to Analog Supply
Simple three-wire serial interface
SPI®and Microwire™ Compatible
Schmitt Trigger on Serial Clock (SCLK)
R/W Calibration Registers Per Channel
Selectable Word Rates: 6.25 to 3,840 Sps
Selectable 50 or 60 Hz Rejection
Power Supply Configurations
VA+ = +5 V; VA- = 0 V; VD+ = +3 V to +5 V
VA+ = +2.5 V; VA- = -2.5 V; VD+ = +3 V to +5 V
VA+ = +3 V; VA- = -3 V; VD+ = +3 V
General Description
The CS5531/32/33/34 are highly integrated ∆Σ Analog-
to-Digital Converters (ADCs) which use charge-balance
techniques to achieve 16-bit (CS5531/33) and 24-bit
(CS5532/34) performance. The ADCs are optimized for
measuring low-level unipolar or bipolar signals in weigh
scale, process control, scientific, and medical
applications.
To accommodate these applications, the ADCs come as
either two-channel (CS5531/32) or four-channel
(CS5533/34) devices and include a very low noise chop-
per-stabilized instrumentation amplifier (6 nV/√Hz @ 0.1
Hz) with selectable gains of 1×, 2×, 4×, 8×, 16×, 32×, and
64×. These ADCs also include a fourth order ∆Σ modu-
lator followed by a digital filter which provides twenty
selectable output word rates of 6.25, 7.5, 12.5, 15, 25, 30,
50, 60, 100, 120, 200, 240, 400, 480, 800, 960, 1600,
1920, 3200, and 3840 Sps (MCLK = 4.9152 MHz).
To ease communication between the ADCs and a micro-
controller, the converters include a simple three-wire se-
rial interface which is SPI and Microwire compatible with
a Schmitt Trigger input on the serial clock (SCLK).
High dynamic range, programmable output rates, and
flexible power supply options makes these ADCs ideal
solutions for weigh scale and process control
applications.
ORDERING INFORMATION
See page 48
VA+ C1 C2 VREF+ VREF-
VD+
AIN1+
AIN1-
AIN2+
AIN2-
AIN3+
AIN3-
AIN4+
AIN4-
MUX
(CS5533/34
SHOWN)
PGIA
1,2,4,8,16
32,64
DIFFERENTIAL
4TH ORDER ∆Σ
MODULATOR
LATCH
PROGRAMMABLE
SINC FIR FILTER
SERIAL
INTERFACE
CLOCK
GENERATOR
CALIBRATION
SRAM/CONTROL
LOGIC
CS
SDI
SDO
SCLK
VA-
A0/GUARD
A1
OSC1 OSC2
DGND
Preliminary Product Information
This document contains information for a new product.
Cirrus Logic reserves the right to modify this product without notice.
P.O. Box 17847, Austin, Texas 78760
(512) 445 7222 FAX: (512) 445 7581
http://www.cirrus.com
©Copyright Cirrus Logic, Inc. 2002
(All Rights Reserved)
MAR ‘02
DS289PP5
1
1 page  
CS5531/32/33/34
1. CHARACTERISTICS AND SPECIFICATIONS
ANALOG CHARACTERISTICS (VA+, VD+ = 5 V ±5%; VREF+ = 5 V; VA-, VREF-, DGND = 0 V;
MCLK = 4.9152 MHz; OWR (Output Word Rate) = 60 Sps; Bipolar Mode; Gain = 32)
(See Notes 1 and 2.)
Accuracy
Linearity Error
No Missing Codes
Bipolar Offset
Unipolar Offset
Offset Drift
Bipolar Full Scale Error
Unipolar Full Scale Error
Full Scale Drift
Parameter
CS5531-AS/CS5533-AS
Min Typ
Max
Unit
- ±0.0015 ±0.003 %FS
16 -
- Bits
- ±1 ±2 LSB16
- ±2 ±4 LSB16
(Notes 3 and 4) - 640/G + 5 -
nV/°C
- ±8 ±31 ppm
- ±16 ±62 ppm
(Note 4) -
2
- ppm/°C
Parameter
Accuracy
Linearity Error
No Missing Codes
Bipolar Offset
Unipolar Offset
Offset Drift
(Notes 3 and 4)
Bipolar Full Scale Error
Unipolar Full Scale Error
Full Scale Drift
(Note 4)
CS5532-AS/CS5534-AS
Min Typ
Max
- ±0.0015 ±0.003
24 -
-
- ±16 ±32
- ±32 ±64
- 640/G + 5 -
- ±8 ±31
- ±16 ±62
- TBD
-
CS5532-BS/CS5534-BS
Min Typ Max
Unit
- ±0.0007 ±0.0015 %FS
24 -
- Bits
- ±16 ±32 LSB24
- ±32 ±64 LSB24
- 640/G + 5 -
nV/°C
- ±8 ±31 ppm
- ±16 ±62 ppm
- 2 - ppm/°C
Notes: 1. Applies after system calibration at any temperature within -40 °C ~ +85 °C.
2. Specifications guaranteed by design, characterization, and/or test. LSB is 16 bits for the CS5531/33 and
LSB is 24 bits for the CS5532/34.
3. This specification applies to the device only and does not include any effects by external parasitic
thermocouples. The PGIA contributes 5 nV of offset drift, and the modulator contributes 640/G nV of
offset drift, where G is the amplifier gain setting.
4. Drift over specified temperature range after calibration at power-up at 25 °C.
DS289PP5
5
5 Page 
CS5531/32/33/34
DYNAMIC CHARACTERISTICS
Parameter
Symbol
Ratio
Unit
Modulator Sampling Rate
Filter Settling Time to 1/2 LSB (Full Scale Step Input)
Single Conversion mode (Notes 22, 23, and 24)
Continuous Conversion mode, OWR < 3200 Sps
Continuous Conversion mode, OWR ≥ 3200 Sps
fs
ts
ts
ts
MCLK/16
1/OWRSC
5/OWRsinc5 + 3/OWR
5/OWR
Sps
s
s
s
22. The ADCs use a Sinc5 filter for the 3200 Sps and 3840 Sps output word rate (OWR) and a Sinc5 filter
followed by a Sinc3 filter for the
(FRS = 0) word rate associated
owtihtherthOeWSRinsc.5OfiWlteRr.sinc5
refers
to
the
3200
Sps
(FRS
=
1)
or
3840
Sps
23. The single conversion mode only outputs fully settled conversions. See Table 1 for more details about
single conversion mode timing. OWRSC is used here to designate the different conversion time
associated with single conversions.
24. The continuous conversion mode outputs every conversion. This means that the filter’s settling time
with a full scale step input in the continuous conversion mode is dictated by the OWR.
ABSOLUTE MAXIMUM RATINGS (DGND = 0 V; See Note 25.)
DC Power Supplies
Parameter
Input Current, Any Pin Except Supplies
Output Current
Power Dissipation
Analog Input Voltage
Digital Input Voltage
Ambient Operating Temperature
Storage Temperature
(Notes 26 and 27)
Positive Digital
Positive Analog
Negative Analog
(Notes 28 and 29)
(Note 30)
VREF pins
AIN Pins
Symbol
VD+
VA+
VA-
IIN
IOUT
PDN
VINR
VINA
VIND
TA
Tstg
Min Typ
Max Unit
-0.3
-
+6.0
V
-0.3
-
+6.0
V
+0.3
-
-3.75
V
- - ±10 mA
- - ±25 mA
- - 500 mW
(VA-) -0.3 - (VA+) + 0.3 V
(VA-) -0.3 - (VA+) + 0.3 V
-0.3 - (VD+) + 0.3 V
-40 -
85 °C
-65 - 150 °C
Notes: 25. All voltages with respect to ground.
26. VA+ and VA- must satisfy {(VA+) - (VA-)} ≤ +6.6 V.
27. VD+ and VA- must satisfy {(VD+) - (VA-)} ≤ +7.5 V.
28. Applies to all pins including continuous overvoltage conditions at the analog input (AIN) pins.
29. Transient current of up to 100 mA will not cause SCR latch-up. Maximum input current for a power
supply pin is ±50 mA.
30. Total power dissipation, including all input currents and output currents.
WARNING: Operation at or beyond these limits may result in permanent damage to the device.
Normal operation is not guaranteed at these extremes.
DS289PP5
11
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet CS5534.PDF ] | |
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