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CS7054 데이터시트 PDF




Cherry Semiconductor Corporation에서 제조한 전자 부품 CS7054은 전자 산업 및 응용 분야에서
광범위하게 사용되는 반도체 소자입니다.


 

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부품번호 CS7054 기능
기능 Low Side PWM FET Controller
제조업체 Cherry Semiconductor Corporation
로고 Cherry Semiconductor Corporation 로고


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CS7054 데이터시트, 핀배열, 회로
CS7054
Low Side PWM FET Controller
Description
The CS7054 is a monolithic integrat-
ed circuit designed primarily to
control the rotor speed of perma-
nent magnet, direct current (DC)
brush motors. It drives the gate of
an N channel power MOSFET or
IGBT with a user-adjustable, fixed
frequency, variable duty cycle,
pulse width modulated (PWM) sig-
nal. The CS7054 can also be used to
control other loads such as incan-
descent bulbs and solenoids.
Inductive current from the motor or
solenoid is recirculated through an
external diode.
The CS7054 accepts a DC level
input signal of 0 to 5V to control the
pulse width of the output signal.
This signal can be generated by a
potentiometer referenced to the on-
chip 5V linear regulator, or a fil-
tered 0% to 100% PWM signal also
referenced to the 5V regulator.
The IC is placed in a sleep state by
pulling the CTL lead below 0.5V. In
this mode everything on the chip is
shut down except for the on-chip
regulator and the overall current
draw is less than 275 µA. There are
a number of on-chip diagnostics
that look for potential failure modes
and can disable the external power
MOSFET.
Features
s 200 mA Peak PWM Gate
Drive Output
s Patented Voltage
Compensation Circuit
s 100% Duty Cycle
Capability
s 5V, ± 3% Linear Reg.
s Low Current Sleep Mode
s Overvoltage Protection
s Over Current Protection
of External MOSFET /
IGBT
s Output Inhibit
Application Diagram
VBAT 42.5mH
1000mF
1000mF
RS
51
10mF
CFLT
COSC
.25mF
390pF
ROSC
105K
OUTPUT VCC
Gnd PGnd
FLT INH
COSC
IADJ
ROSC ISENSE+
CTL ISENSE-
NC VREG
Input
10K
10K
P1
100K
10K
10K
N1 10K
10mF
10K
RGATE
6
.01mF
1M
MOT+
MOT-
RCS1
CCS 51
.022mF
RCS2
51
RSENSE
4mW
Package Options
14 Lead PDIP
OUTPUT 1
Gnd 2
FLT 3
COSC 4
ROSC 5
CTL 6
NC 7
14 VCC
13 PGnd
12 INH
11 IADJ
10 ISENSE+
9 ISENSE-
8 VREG
Consult factory for 16 lead SO
wide package.
Rev. 4/21/99
Cherry Semiconductor Corporation
2000 South County Trail, East Greenwich, RI 02818
Tel: (401)885-3600 Fax: (401)885-5786
Web Site: www.cherry-semi.com
1
A Company
¨




CS7054 pdf, 반도체, 판매, 대치품
Application Information: continued
in the supply voltage. The duty cycle is varied based upon
the input voltage and supply voltage by the following
equation:
tial voltage across these two leads is amplified internally
and compared to the voltage at the IADJ lead. The gain, AV,
is set internally and externally by the following equation:
Duty Cycle = 100% ´ 2.8 ´ VCTL
VCC
AV =
VI(ADJ)
ISENSE+ - ISENSE-
37000
=
1000 + RCS
An internal DC voltage equal to:
VDC = (1.683 ´ VCTL) + (VVALLEY)
is compared to the oscillator voltage to produce the com-
pensated duty cycle. The transfer is set up so that at VCC =
14V the duty will equal VCTL divided by VREG. For exam-
ple at VCC = 14V, VREG = 5V and VCTL = 2.5V, the duty
cycle would be 50% at the output. This would place a 7V
average voltage across the load. If VCC then drops to 10V,
the IC would change the duty cycle to 70% and hence keep
the average load voltage at 7V.
120%
100%
VCC = 8V
80%
60%
40%
VCC = 14V
VCC = 16V
20%
0%
10%
20%
30%
40% 50% 60% 70%
CTL Voltage (% of VREG)
80%
90% 100%
Figure 1: Voltage Compensation
5V Linear Regulator
There is a 5V, 5mA linear regulator available at the VREG
lead for external use. This voltage acts as a reference for
many internal and external functions. It has a drop out of
approximately 1.5V at room temperature and does not
require an external capacitor for stability.
Current Sense and Timer
The IC differentially monitors the load current on a cycle
by cycle basis at the ISENSE+ and ISENSE- leads. The differen-
The current limit (ILIM) is set by the external current sense
resistor (RSENSE) placed across the ISENSE+ and ISENSE- ter-
minals and the voltage at the IADJ lead.
ILIM =
(1000 + RCS)
37000
´
VI(ADJ)
RSENSE
The RCS resistors and CCS components form a differential
low pass filter which filters out high frequency noise gen-
erated by the switching of the external MOSFET and the
associated lead noise. RCS also forms an error term in the
gain of the ILIM equation because the ISENSE+ and ISENSE-
leads are low impedance inputs thereby creating a good
current sensing amplifier. Both leads source 50µA while
the chip is in run mode. RCS should be much less than 1000
½ to minimize error in the ILIM equation. IADJ should be
biased between 1V and 4V.
When the current through the external MOSFET exceeds
ILIM, an internal latch is set and the output pulls the gate of
the MOSFET low for the remainder of the oscillator cycle
(fault mode). At the start of the next cycle, the latch is reset
and the IC reverts back to run mode until another fault
occurs. If a number of faults occur in a given period of
time, the IC Òtimes outÓ and disables the MOSFET for a
long period of time to let it cool off. This is accomplished
by charging the CFLT capacitor each time an over current
condition occurs. If a cycle goes by with no overcurrent
fault occurring, an even smaller amount of charge will be
removed from CFLT. If enough faults occur together, even-
tually CFLT will charge up to 2.4V and the fault latch will
be set. The fault latch will not be reset until the CFLT dis-
charges to 0.6V. This action will continue indefinitely if the
fault persists.
The off time and on time are set by the following:
Off Time = CFLT ´ 2.4V - 0.6V
4.5µA
4

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구매 문의
일반 IC 문의 : 샘플 및 소량 구매
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IGBT, TR 모듈, SCR 및 다이오드 모듈을 포함한
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