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PDF CS8126-1YTVA5 Data sheet ( Hoja de datos )
| Número de pieza | CS8126-1YTVA5 | |
| Descripción | 5V/ 750mA Low Dropout Linear Regulator with Delayed RESET | |
| Fabricantes | Cherry Semiconductor Corporation | |
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CS8126,-1,-2
5V, 750mA Low Dropout Linear Regulator
with Delayed RESET
Description
Features
The CS8126 is a low dropout, high cur-
rent 5V linear regulator. It is an
improved replacement for the CS8156.
Improvements include higher accuracy,
tighter saturation control, better supply
rejection, and enhanced RESET circuit-
ry. Familiar PNP regulator features
such as reverse battery protection, over-
voltage shutdown, thermal shutdown,
and current limit make the CS8126 suit-
able for use in automotive and battery
operated equipment. Additional on-
chip filtering has been included to
enhance rejection of high frequency
transients on all external leads.
An active microprocessor RESET func-
tion is included on-chip with externally
programmable delay time. During
power-up, or after detection of any
error in the regulated output,
the RESET lead will remain in the low
state for the duration of the delay.
Types of errors include short circuit,
low input voltage, overvoltage shut-
down, thermal shutdown, or others that
cause the output to become unregulat-
ed. This function is independent of the
input voltage and will function correct-
ly with an output voltage as low as 1V.
Hysteresis is included in both the reset
and Delay comparators for enhanced
noise immunity. A latching discharge
circuit is used to discharge the Delay
capacitor, even when triggered by a rel-
atively short fault condition. This circuit
improves upon the commonly used
SCR structure by providing full capaci-
tor discharge (0.2V type).
Note:The CS8126 is lead compatible
with the LM2925, TLE4260, L4947,
LM2927, and LM2926.
Block Diagram
Over Voltage
Shutdown
Pre-
Regulator
Regulated Supply
for Circuit Bias
Bandgap
Reference
Charge
Current
Generator
Thermal
Shutdown
Error
Amp
Anti-Saturation
and
Current Limit
VIN
VOUT
s Low Dropout Voltage
(0.6V at 0.5A)
s 3% Output Accuracy
s Active RESET
s External RESET Delay
for Reset
s Protection Circuitry
Reverse Battery
Protection
+60V, -50V Peak
Transient Voltage
Short Circuit Protection
Internal Thermal
Overload Protection
Package Options
16 Lead SOIC Wide
VIN 1
NC
VOUT
NC
NC VOUT(SENSE)
NC NC
NC
ÐRÐEÐSÐEÐTÐ
NC
NC
Gnd
NC
Delay
NC
7 L D2PAK
Tab (Gnd)
5 L TO-220
Tab (Gnd)
Delay
Gnd
Latching
Discharge
QS
R
-
+
Reset
Comparator
VDischarge
Delay
+ Comparator
-
RESET
1
1 VIN
2 VOUT
3 VOUT(SENSE)
4 Gnd
5 Delay
6 RESET
7 NC
1
CS8126-1
1 VIN
2 VOUT
3 Gnd
4 Delay
5 RESET
CS8126-2
1 VIN
2 RESET
3 Gnd
4 Delay
5 VOUT
Rev. 5/4/99
Cherry Semiconductor Corporation
2000 South County Trail, East Greenwich, RI 02818
Tel: (401)885-3600 Fax: (401)885-5786
Email: [email protected]
Web Site: www.cherry-semi.com
1 A ¨ Company
1 page  
VOUT
VRT(ON)
VRT(OFF)
VRH
RESET
(3)
VRL
Delay
VDC(HI)
VDC(LO)
VDH
RESET Circuit Waveform
(1)
(2)
tDelay
(2)
(1) = No Delay Capacitor
(2) = With Delay Capacitor
(3) = Max: RESET Voltage (1.0V)
VDIS
Circuit Description
The CS8126 RESET function, has hysteresis on both the
Reset and Delay comparators, a latching Delay capacitor
discharge circuit, and operates down to 1V.
The RESET circuit output is an open collector type with
ON and OFF parameters as specified. The RESET output
NPN transistor is controlled by the two circuits described
(see Block Diagram).
Low Voltage Inhibit Circuit
This circuit monitors output voltage, and when the output
voltage falls below VRT(OFF), causes the RESET output tran-
sistor to be in the ON (saturation) state. When the output
voltage rises above VRT(ON), this circuit permits the RESET
output transistor to go into the OFF state if allowed by
the RESET Delay circuit.
RESET Delay Circuit
This circuit provides a programmable (by external capaci-
tor) delay on the RESET output lead. The Delay lead pro-
vides source current to the external delay capacitor only
when the "Low Voltage Inhibit" circuit indicates that out-
put voltage is above VRT(ON). Otherwise, the Delay lead
sinks current to ground (used to discharge the delay
capacitor). The discharge current is latched ON when the
output voltage falls below VRT(OFF). The Delay capacitor is
fully discharged anytime the output voltage falls out of
regulation, even for a short period of time. This feature
ensures a controlled RESET pulse is generated following
detection of an error condition. The circuit allows
the RESET output transistor to go to the OFF (open) state
only when the voltage on the Delay lead is higher than
VDC(H1).
The Delay time for the RESET function is calculated from
the formula:
Delay time =
CDelay ´ VDelay Threshold
ICharge
Delay time = CDelay ´ 3.2 ´ 105
If CDelay = 0.1µF, Delay time (ms) = 32ms ± 50%: i.e. 16ms
to 48ms. The tolerance of the capacitor must be taken into
account to calculate the total variation in the delay time.
5
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| Páginas | Total 9 Páginas | |
| PDF Descargar | [ Datasheet CS8126-1YTVA5.PDF ] | |
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