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부품번호 CS82C54 기능
기능 CMOS Programmable Interval Timer
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CS82C54 데이터시트, 핀배열, 회로
82C54
March 1997
CMOS Programmable Interval Timer
Features
Description
• 8MHz to 12MHz Clock Input Frequency
• Compatible with NMOS 8254
- Enhanced Version of NMOS 8253
• Three Independent 16-Bit Counters
• Six Programmable Counter Modes
• Status Read Back Command
• Binary or BCD Counting
• Fully TTL Compatible
• Single 5V Power Supply
• Low Power
- ICCSB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10µA
- ICCOP . . . . . . . . . . . . . . . . . . . . . . . . . . 10mA at 8MHz
• Operating Temperature Ranges
- C82C54 . . . . . . . . . . . . . . . . . . . . . . . . . .0oC to +70oC
- I82C54 . . . . . . . . . . . . . . . . . . . . . . . . . -40oC to +85oC
- M82C54 . . . . . . . . . . . . . . . . . . . . . . . -55oC to +125oC
The Intersil 82C54 is a high performance CMOS Program-
mable Interval Timer manufactured using an advanced 2
micron CMOS process.
The 82C54 has three independently programmable and
functional 16-bit counters, each capable of handling clock
input frequencies of up to 8MHz (82C54) or 10MHz
(82C54-10) or 12MHz (82C54-12).
The high speed and industry standard configuration of the
82C54 make it compatible with the Intersil 80C86, 80C88,
and 80C286 CMOS microprocessors along with many other
industry standard processors. Six programmable timer
modes allow the 82C54 to be used as an event counter,
elapsed time indicator, programmable one-shot, and many
other applications. Static CMOS circuit design insures low
power operation.
The Intersil advanced CMOS process results in a significant
reduction in power with performance equal to or greater than
existing equivalent products.
Pinouts
82C54 (PDIP, CERDIP, SOIC)
TOP VIEW
D7 1
D6 2
D5 3
D4 4
D3 5
D2 6
D1 7
D0 8
CLK 0 9
OUT 0 10
GATE 0 11
GND 12
24 VCC
23 WR
22 RD
21 CS
20 A1
19 A0
18 CLK 2
17 OUT 2
16 GATE 2
15 CLK 1
14 GATE 1
13 OUT 1
82C54 (PLCC/CLCC)
TOP VIEW
4 3 2 1 28 27 26
D4 5
D3 6
D2 7
D1 8
D0 9
CLK 0 10
NC 11
25 NC
24 CS
23 A1
22 A0
21 CLK2
20 OUT 2
19 GATE 2
12 13 14 15 16 17 18
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
http://www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 1999
4-1
File Number 2970.1




CS82C54 pdf, 반도체, 판매, 대치품
82C54
Control Word Register
The Control Word Register (Figure 2) is selected by the
Read/Write Logic when A1, A0 = 11. If the CPU then does a
write operation to the 82C54, the data is stored in the Con-
trol Word Register and is interpreted as a Control Word used
to define the Counter operation.
The Control Word Register can only be written to; status
information is available with the Read-Back Command.
INTERNAL BUS
CONTROL
WORD
REGISTER
STATUS
LATCH
STATUS
REGISTER
CRM
CRL
D7 - D0 8
DATA/
BUS
BUFFER
COUNTER
0
CLK 0
GATE 0
OUT 0
CONTROL
LOGIC
CE
OLM
OLL
RD
WR
READ/
WRITE
A0 LOGIC
A1
CS
CONTROL
WORD
REGISTER
COUNTER
1
CLK 1
GATE 1
OUT 1
COUNTER
2
CLK 2
GATE 2
OUT 2
FIGURE 2. CONTROL WORD REGISTER AND COUNTER
FUNCTIONS
Counter 0, Counter 1, Counter 2
These three functional blocks are identical in operation, so
only a single Counter will be described. The internal block
diagram of a signal counter is shown in Figure 3. The
counters are fully independent. Each Counter may operate
in a different Mode.
The Control Word Register is shown in the figure; it is not
part of the Counter itself, but its contents determine how the
Counter operates.
The status register, shown in the figure, when latched, con-
tains the current contents of the Control Word Register and
status of the output and null count flag. (See detailed expla-
nation of the Read-Back command.)
The actual counter is labeled CE (for Counting Element). It is
a 16-bit presettable synchronous down counter.
GATE n
CLK n OUT n
FIGURE 3. COUNTER INTERNAL BLOCK DIAGRAM
OLM and OLL are two 8-bit latches. OL stands for “Output
Latch”; the subscripts M and L for “Most significant byte” and
“Least significant byte”, respectively. Both are normally referred
to as one unit and called just OL. These latches normally “fol-
low” the CE, but if a suitable Counter Latch Command is sent to
the 82C54, the latches “latch” the present count until read by
the CPU and then return to “following” the CE. One latch at a
time is enabled by the counter’s Control Logic to drive the inter-
nal bus. This is how the 16-bit Counter communicates over the
8-bit internal bus. Note that the CE itself cannot be read; when-
ever you read the count, it is the OL that is being read.
Similarly, there are two 8-bit registers called CRM and CRL (for
“Count Register”). Both are normally referred to as one unit and
called just CR. When a new count is written to the Counter, the
count is stored in the CR and later transferred to the CE. The
Control Logic allows one register at a time to be loaded from
the internal bus. Both bytes are transferred to the CE simulta-
neously. CRM and CRL are cleared when the Counter is pro-
grammed for one byte counts (either most significant byte only
or least significant byte only) the other byte will be zero. Note
that the CE cannot be written into; whenever a count is written,
it is written into the CR.
The Control Logic is also shown in the diagram. CLK n,
GATE n, and OUT n are all connected to the outside world
through the Control Logic.
82C54 System Interface
The 82C54 is treated by the system software as an array of
peripheral I/O ports; three are counters and the fourth is a
control register for MODE programming.
Basically, the select inputs A0, A1 connect to the A0, A1
address bus signals of the CPU. The CS can be derived
directly from the address bus using a linear select method or
it can be connected to the output of a decoder.
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CS82C54 전자부품, 판매, 대치품
82C54
1. Read least significant byte.
2. Write new least significant byte.
3. Read most significant byte.
4. Write new most significant byte.
If a counter is programmed to read or write two-byte counts,
the following precaution applies: A program MUST NOT
transfer control between reading the first and second byte to
another routine which also reads from that same Counter.
Otherwise, an incorrect count will be read.
Read-Back Command
The read-back command allows the user to check the count
value, programmed Mode, and current state of the OUT pin
and Null Count flag of the selected counter(s).
The command is written into the Control Word Register and
has the format shown in Figure 5. The command applies to
the counters selected by setting their corresponding bits D3,
D2, D1 = 1.
A0, A1 = 11; CS = 0; RD = 1; WR = 0
D7 D6
D5
D4 D3 D2 D1 D0
1 1 COUNT STATUS CNT 2 CNT 1 CNT 0 0
D5: 0 = Latch count of selected Counter (s)
D4: 0 = Latch status of selected Counter(s)
D3: 1 = Select Counter 2
D2: 1 = Select Counter 1
D1: 1 = Select Counter 0
D0: Reserved for future expansion; Must be 0
FIGURE 5. READ-BACK COMMAND FORMAT
The read-back command may be used to latch multiple
counter output latches (OL) by setting the COUNT bit D5 = 0
and selecting the desired counter(s). This signal command
is functionally equivalent to several counter latch commands,
one for each counter latched. Each counter’s latched count
is held until it is read (or the counter is reprogrammed). That
counter is automatically unlatched when read, but other
counters remain latched until they are read. If multiple count
read-back commands are issued to the same counter with-
out reading the count, all but the first are ignored; i.e., the
count which will be read is the count at the time the first
read-back command was issued.
The read-back command may also be used to latch status
information of selected counter(s) by setting STATUS bit D4
= 0. Status must be latched to be read; status of a counter is
accessed by a read from that counter.
The counter status format is shown in Figure 6. Bits D5
through D0 contain the counter’s programmed Mode exactly
as written in the last Mode Control Word. OUTPUT bit D7
contains the current state of the OUT pin. This allows the
user to monitor the counter’s output via software, possibly
eliminating some hardware from a system.
D7 D6 D5 D4 D3 D2 D1 D0
OUTPUT NULL RW1 RW0 M2 M1 M0 BCD
COUNT
D7: 1 = Out pin is 1
0 = Out pin is 0
D6: 1 = Null count
0 = Count available for reading
D5 - D0 = Counter programmed mode (See Control Word Formats)
FIGURE 6. STATUS BYTE
NULL COUNT bit D6 indicates when the last count written to
the counter register (CR) has been loaded into the counting
element (CE). The exact time this happens depends on the
Mode of the counter and is described in the Mode Definitions,
but until the counter is loaded into the counting element (CE),
it can’t be read from the counter. If the count is latched or read
before this time, the count value will not reflect the new count
just written. The operation of Null Count is shown below.
THIS ACTION:
CAUSES:
A. Write to the control word register:(1) . . . . . . . . . . Null Count = 1
B. Write to the count register (CR):(2) . . . . . . . . . . . Null Count = 1
C. New count is loaded into CE (CR - CE) . . . . . . . . Null Count = 0
(1) Only the counter specified by the control word will have its null
count set to 1. Null count bits of other counters are unaffected.
(2) If the counter is programmed for two-byte counts (least signifi-
cant byte then most significant byte) null count goes to 1 when
the second byte is written.
If multiple status latch operations of the counter(s) are per-
formed without reading the status, all but the first are ignored;
i.e., the status that will be read is the status of the counter at
the time the first status read-back command was issued.
COMMANDS
D7 D6 D5 D4 D3 D2 D1 D0
DESCRIPTION
RESULT
1 1 0 0 0 0 1 0 Read-Back Count and Status of Counter 0 Count and Status Latched for Counter 0
1 1 1 0 0 1 0 0 Read-Back Status of Counter 1
Status Latched for Counter 1
1 1 1 0 1 1 0 0 Read-Back Status of Counters 2, 1
Status Latched for Counter 2,
But Not Counter 1
1 1 0 1 1 0 0 0 Read-Back Count of Counter 2
Count Latched for Counter 2
1 1 0 0 0 1 0 0 Read-Back Count and Status of Counter 1 Count Latched for Counter 1,
But Not Status
1 1 1 0 0 0 1 0 Read-Back Status of Counter 1
Command Ignored, Status Already
Latched for Counter 1
FIGURE 7. READ-BACK COMMAND EXAMPLE
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