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부품번호 CS82C59A-12 기능
기능 CMOS Priority Interrupt Controller
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CS82C59A-12 데이터시트, 핀배열, 회로
82C59A
March 1997
CMOS Priority Interrupt Controller
Features
Description
• 12.5MHz, 8MHz and 5MHz Versions Available
- 12.5MHz Operation . . . . . . . . . . . . . . . . . . . 82C59A-12
- 8MHz Operation . . . . . . . . . . . . . . . . . . . . . . . 82C59A
- 5MHz Operation . . . . . . . . . . . . . . . . . . . . . . 82C59A-5
• High Speed, “No Wait-State” Operation with 12.5MHz
80C286 and 8MHz 80C86/88
• Pin Compatible with NMOS 8259A
• 80C86/88/286 and 8080/85/86/88/286 Compatible
• Eight-Level Priority Controller, Expandable to
64 Levels
• Programmable Interrupt Modes
• Individual Request Mask Capability
• Fully Static Design
• Fully TTL Compatible
• Low Power Operation
- ICCSB . . . . . . . . . . . . . . . . . . . . . . . . . 10µA Maximum
- ICCOP . . . . . . . . . . . . . . . . . . . . . 1mA/MHz Maximum
The Intersil 82C59A is a high performance CMOS Priority
Interrupt Controller manufactured using an advanced 2µm
CMOS process. The 82C59A is designed to relieve the sys-
tem CPU from the task of polling in a multilevel
priority system. The high speed and industry standard
configuration of the 82C59A make it compatible with micro-
processors such as 80C286, 80286, 80C86/88, 8086/88,
8080/85 and NSC800.
The 82C59A can handle up to eight vectored priority inter-
rupting sources and is cascadable to 64 without additional
circuitry. Individual interrupting sources can be masked or
prioritized to allow custom system configuration. Two modes
of operation make the 82C59A compatible with both 8080/85
and 80C86/88/286 formats.
Static CMOS circuit design ensures low operating power.
The Intersil advanced CMOS process results in performance
equal to or greater than existing equivalent products at a
fraction of the power.
• Single 5V Power Supply
• Operating Temperature Ranges
- C82C59A . . . . . . . . . . . . . . . . . . . . . . . . .0oC to +70oC
- I82C59A . . . . . . . . . . . . . . . . . . . . . . . . -40oC to +85oC
- M82C59A . . . . . . . . . . . . . . . . . . . . . . -55oC to +125oC
Ordering Information
5MHz
CP82C59A-5
IP82C59A-5
CS82C59A-5
IS82C59A-5
CD82C59A-5
ID82C59A-5
MD82C59A-5/B
5962-8501601YA
MR82C59A-5/B
5962-85016013A
CM82C59A-5
PART NUMBER
8MHz
CP82C59A
IP82C59A
CS82C59A
IS82C59A
CD82C59A
ID82C59A
MD82C59A/B
5962-8501602YA
MR82C59A/B
5962-85016023A
CM82C59A
12.5MHz
CP82C59A-12
IP82C59A-12
CS82C59A-12
IS82C59A-12
CD82C59A-12
ID82C59A-12
MD82C59A-12/B
-
MR82C59A-12/B
-
CM82C59A-12
PACKAGE
28 Ld PDIP
28 Ld PLCC
CERDIP
SMD#
28 Pad CLCC
SMD#
28 Ld SOIC
TEMPERATURE
RANGE
0oC to +70oC
-40oC to +85oC
0oC to +70oC
-40oC to +85oC
0oC to +70oC
-40oC to +85oC
-55oC to +125oC
-55oC to +125oC
0oC to +70oC
PKG. NO.
E28.6
E28.6
N28.45
N28.45
F28.6
F28.6
F28.6
F28.6
J28.A
J28.A
M28.3
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
http://www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 1999
4-1
File Number 2784.2




CS82C59A-12 pdf, 반도체, 판매, 대치품
82C59A
A more desirable method would be one that would allow the
microprocessor to be executing its main program and only
stop to service peripheral devices when it is told to do so by
the device itself. In effect, the method would provide an
external asynchronous input that would inform the processor
that it should complete whatever instruction that is currently
being executed and fetch a new routine that will service the
requesting device. Once this servicing is complete, however,
the processor would resume exactly where it left off.
This is the Interrupt-driven method. It is easy to see that sys-
tem throughput would drastically increase, and thus, more
tasks could be assumed by the microcomputer to further
enhance its cost effectiveness.
INT
CPU
The Programmable Interrupt Controller (PlC) functions as an
overall manager in an Interrupt-Driven system. It accepts
requests from the peripheral equipment, determines which
of the incoming requests is of the highest importance (prior-
ity), ascertains whether the incoming request has a higher
priority value than the level currently being serviced, and
issues an interrupt to the CPU based on this determination.
Each peripheral device or structure usually has a special
program or “routine” that is associated with its specific func-
tional or operational requirements; this is referred to as a
“service routine”. The PlC, after issuing an interrupt to the
CPU, must somehow input information into the CPU that can
“point” the Program Counter to the service routine associ-
ated with the requesting device. This “pointer” is an address
in a vectoring table and will often be referred to, in this docu-
ment, as vectoring data.
RAM
ROM
PIC
I/O (1)
I/O (2)
I/O (N)
FIGURE 3. INTERRUPT METHOD
82C59A Functional Description
The 82C59A is a device specifically designed for use in real
time, interrupt driven microcomputer systems. It manages
eight levels of requests and has built-in features for expand-
ability to other 82C59As (up to 64 levels). It is programmed
by system software as an I/O peripheral. A selection of prior-
ity modes is available to the programmer so that the manner
in which the requests are processed by the 82C59A can be
configured to match system requirements. The priority
modes can be changed or reconfigured dynamically at any
time during main program operation. This means that the
complete interrupt structure can be defined as required,
based on the total system environment.
Interrupt Request Register (IRR) and In-Service Register
(ISR)
The interrupts at the IR input lines are handled by two registers
in cascade, the Interrupt Request Register (lRR) and the In-
Service Register (lSR). The IRR is used to indicate all the inter-
rupt levels which are requesting service, and the ISR is used to
store all the interrupt levels which are currently being serviced.
D7 - D0
DATA
BUS
BUFFER
INTA
INT
CONTROL LOGIC
RD
WR
A0
CS
CAS 0
CAS 1
CAS 2
SP/EN
READ/
WRITE
LOGIC
CASCADE
BUFFER
COMPARATOR
IN
SERVICE
REG
(ISR)
PRIORITY
RESOLVER
INTERRUPT
REQUEST
REG
(IRR)
INTERRUPT MASK REG
(IMR)
IR0
IR1
IR2
IR3
IR4
IR5
IR6
IR7
INTERNAL BUS
FIGURE 4. 82C59A FUNCTIONAL DIAGRAM
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CS82C59A-12 전자부품, 판매, 대치품
82C59A
CONTENT OF THIRD INTERRUPT VECTOR BYTE
Initialization Command Words (lCWs)
D7 D6 D5 D4 D3 D2
A15 A14 A13 A12 A11 A10
D1
A9
D0
A8
80C86, 8OC88, 80C286 Interrupt Response Mode
80C86/88/286 mode is similar to 8080/85 mode except that
only two Interrupt Acknowledge cycles are issued by the pro-
cessor and no CALL opcode is sent to the processor. The
first interrupt acknowledge cycle is similar to that of 8080/85
systems in that the 82C59A uses it to internally freeze the
state of the interrupts for priority resolution and, as a master,
it issues the interrupt code on the cascade lines. On this first
cycle, it does not issue any data to the processor and leaves
its data bus buffers disabled. On the second interrupt
acknowledge cycle in the 86/88/286 mode, the master (or
slave if so programmed) will send a byte of data to the pro-
cessor with the acknowledged interrupt code composed as
follows (note the state of the ADI mode control is ignored
and A5 - A11 are unused in the 86/88/286 mode).
General
Whenever a command is issued with A0 = 0 and D4 = 1, this
is interpreted as Initialization Command Word 1 (lCW1).
lCW1 starts the initialization sequence during which the fol-
lowing automatically occur:
a. The edge sense circuit is reset, which means that follow-
ing initialization, an interrupt request (IR) input must make
a low-to-high transition to generate an interrupt.
b. The Interrupt Mask Register is cleared.
c. lR7 input is assigned priority 7.
d. Special Mask Mode is cleared and Status Read is set to
lRR.
e. If lC4 = 0, then all functions selected in lCW4 are set to
zero. (Non-Buffered mode (see note), no Auto-EOI,
8080/85 system).
CONTENT OF INTERRUPT VECTOR BYTE FOR
80C86/88/286 SYSTEM MODE
D7 D6 D5 D4 D3 D2 D1 D0
lR7 T7 T6 T5 T4 T3 1 1 1
lR6 T7 T6 T5 T4 T3 1 1 0
IR5 T7 T6 T5 T4 T3 1 0 1
IR4 T7 T6 T5 T4 T3 1 0 0
IR3 T7 T6 T5 T4 T3 0 1 1
IR2 T7 T6 T5 T4 T3 0 1 0
IR1 T7 T6 T5 T4 T3 0 0 1
IR0 T7 T6 T5 T4 T3 0 0 0
NOTE: Master/Slave in ICW4 is only used in the buffered mode.
ICW1
ICW2
NO (SNGL = 1)
IN
CASCADE
MODE
YES (SNGL = 0))
Programming the 82C59A
The 82C59A accepts two types of command words gener-
ated by the CPU:
1. Initialization Command Words (ICWs): Before normal
operation can begin, each 82C59A in the system must be
brought to a starting point - by a sequence of 2 to 4 bytes
timed by WR pulses.
2. Operation Command Words (OCWs): These are the
command words which command the 82C59A to operate
in various interrupt modes. Among these modes are:
NO (IC4 = 0)
ICW3
IS ICW4
NEEDED
YES (IC4 = 1)
ICW4
a. Fully nested mode.
b. Rotating priority mode.
READY TO ACCEPT
INTERRUPT REQUESTS
c. Special mask mode.
d. Polled mode.
The OCWs can be written into the 82C59A anytime after ini-
tialization.
FIGURE 6. 82C59A INITIALIZATION SEQUENCE
Initialization Command Words 1 and 2 (ICW1, lCW2)
A5 - A15: Page starting address of service routines. In an
8080/85 system the 8 request levels will generate CALLS to
8 locations equally spaced in memory. These can be pro-
grammed to be spaced at intervals of 4 or 8 memory loca-
tions, thus, the 8 routines will occupy a page of 32 or 64
bytes, respectively.
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부품번호상세설명 및 기능제조사
CS82C59A-12

CMOS Priority Interrupt Controller

Intersil Corporation
Intersil Corporation

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