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부품번호 CS82C84A 기능
기능 CMOS Clock Generator Driver
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CS82C84A 데이터시트, 핀배열, 회로
Data Sheet
September 9, 2015
82C84A
FN2974.4
CMOS Clock Generator Driver
The Intersil 82C84A is a high performance CMOS Clock
Generator-driver which is designed to service the requirements
of both CMOS and NMOS microprocessors such as the
80C86, 80C88, 8086 and the 8088. The chip contains a crystal
controlled oscillator, a divide-by-three counter and complete
“Ready” synchronization and reset logic.
Static CMOS circuit design permits operation with an external
frequency source from DC to 25MHz. Crystal controlled
operation to 25MHz is guaranteed with the use of a parallel,
fundamental mode crystal and two small load capacitors.
All inputs (except X1 and RES) are TTL compatible over
temperature and voltage ranges.
Power consumption is a fraction of that of the equivalent
bipolar circuits. This speed-power characteristic of CMOS
permits the designer to custom tailor his system design with
respect to power and/or speed requirements.
Features
• Generates the System Clock For CMOS or NMOS
Microprocessors
• Up to 25MHz Operation
• Uses a Parallel Mode Crystal Circuit or External
Frequency Source
• Provides Ready Synchronization
• Generates System Reset Output From Schmitt Trigger
Input
• TTL Compatible Inputs/Outputs
• Very Low Power Consumption
• Single 5V Power Supply
• Operating Temperature Ranges
- C82C84A . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to +70°C
- I82C84A . . . . . . . . . . . . . . . . . . . . . . . . . -40°C to +85°C
- M82C84A . . . . . . . . . . . . . . . . . . . . . . . -55°C to +125°C
• Pb-Free Plus Anneal Available (RoHS Compliant)
Pinouts
82C84A
(PDIP, CERDIP)
TOP VIEW
CSYNC 1
PCLK 2
AEN1 3
RDY1 4
READY 5
RDY2 6
AEN2 7
CLK 8
GND 9
18 VCC
17 X1
16 X2
15 ASYNC
14 EFI
13 F/C
12 OSC
11 RES
10 RESET
82C84A (PLCC, CLCC)
TOP VIEW
RDY1
READY
RDY2
AEN2
NC
4
5
6
7
8
NO
LON3GER2AVAIL1ABL2E0OR1S9UPP11111O54876RTENFEXAD/F2CSCIYNC
9 10 11 12 13
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Copyright Intersil Americas LLC 1997, 2002, 2005, 2015. All Rights Reserved
Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries.
All other trademarks mentioned are the property of their respective owners.




CS82C84A pdf, 반도체, 판매, 대치품
82C84A
Pin Description
SYMBOL NUMBER
TYPE
DESCRIPTION
AEN1,
AEN2
3, 7
I ADDRESS ENABLE: AEN is an active LOW signal. AEN serves to qualify its respective Bus Ready
Signal (RDY1 or RDY2). AEN1 validates RDY1 while AEN2 validates RDY2. Two AEN signal inputs are
useful in system configurations which permit the processor to access two Multi-Master System Busses.
In non-Multi-Master configurations, the AEN signal inputs are tied true (LOW).
RDY1,
RDY2
4, 6
I BUS READY (Transfer Complete). RDY is an active HIGH signal which is an indication from a device
located on the system data bus that data has been received, or is available RDY1 is qualified by AEN1
while RDY2 is qualified by AEN2.
ASYNC
15
I READY SYNCHRONIZATION SELECT: ASYNC is an input which defines the synchronization mode of
the READY logic. When ASYNC is low, two stages of READY synchronization are provided. When
ASYNC is left open or HIGH, a single stage of READY synchronization is provided.
READY
5
O READY: READY is an active HIGH signal which is the synchronized RDY signal input. READY is
cleared after the guaranteed hold time to the processor has been met.
X1, X2
17, 16
I O CRYSTAL IN: X1 and X2 are the pins to which a crystal is attached. The crystal frequency is 3 times
the desired processor clock frequency, (Note 1).
F/C 13
I FREQUENCY/CRYSTAL SELECT: F/C is a strapping option. When strapped LOW. F/C permits the
processor’s clock to be generated by the crystal. When F/C is strapped HIGH, CLK is generated for the
EFI input, (Note 1).
EFI 14
I EXTERNAL FREQUENCY IN: When F/C is strapped HIGH, CLK is generated from the input frequency
appearing on this pin. The input signal is a square wave 3 times the frequency of the desired CLK
output.
CLK 8
O PROCESSOR CLOCK: CLK is the clock output used by the processor and all devices which directly
connect to the processor’s local bus. CLK has an output frequency which is 1/3 of the crystal or EFI
input frequency and a 1/3 duty cycle.
PCLK
2
O PERIPHERAL CLOCK: PCLK is a peripheral clock signal whose output frequency is 1/2 that of CLK
and has a 50% duty cycle.
OSC
12
O OSCILLATOR OUTPUT: OSC is the output of the internal oscillator circuitry. Its frequency is equal to
that of the crystal.
RES
11
I RESET IN: RES is an active LOW signal which is used to generate RESET. The 82C84A provides a
Schmitt trigger input so that an RC connection can be used to establish the power-up reset of proper
duration.
RESET
10
O RESET: RESET is an active HIGH signal which is used to reset the 80C86 family processors. Its timing
characteristics are determined by RES.
CSYNC
1
I CLOCK SYNCHRONIZATION: CSYNC is an active HIGH signal which allows multiple 82C84As to be
synchronized to provide clocks that are in phase. When CSYNC is HIGH the internal counters are reset.
When CSYNC goes LOW the internal counters are allowed to resume counting. CSYNC needs to be
externally synchronized to EFI. When using the internal oscillator CSYNC should be hardwired to
ground.
GND
9
Ground
VCC
18
VCC: The +5V power supply pin. A 0.1F capacitor between VCC and GND is recommended for
decoupling.
NOTE:
1. If the crystal inputs are not used X1 must be tied to VCC or GND and X2 should be left open.
4 FN2974.4
September 9, 2015

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CS82C84A 전자부품, 판매, 대치품
82C84A
Absolute Maximum Ratings
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +8.0V
Input, Output or I/O Voltage . . . . . . . . . . . . GND -0.5V to VCC +0.5V
ESD Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class 1
Operating Conditions
Operating Voltage Range. . . . . . . . . . . . . . . . . . . . . . +4.5V to +5.5V
Operating Temperature Range
C82C84A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0oC to +70oC
I82C84A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40oC to +85oC
M82C84A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -55oC to +125oC
Thermal Information
Thermal Resistance. . . . . . . . . . . . . . . . . JA (oC/W) JC (oC/W)
CERDIP Package. . . . . . . . . . . . . . . . .
80
20
CLCC Package . . . . . . . . . . . . . . . . . .
95
28
PDIP Package* . . . . . . . . . . . . . . . . . .
85
N/A
PLCC Package. . . . . . . . . . . . . . . . . . .
85
N/A
Storage Temperature Range . . . . . . . . . . . . . . . . . -65oC to +150oC
Max Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . .+175oC
Lead Temperature (Soldering 10s) . . . . . . . . . . . . . . . . . . . .+300oC
(PLCC - Lead Tips Only)
*Pb-free PDIPs can be used for through hole wave solder processing
only. They are not intended for use in Reflow solder processing
applications.
Die Characteristics
Gate Count . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50 Gates
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
DC Electrical Specifications VCC = +5.0V10%,
TA = 0oC to +70oC (C82C84A),
TA = -40oC to +85oC (I82C84A),
TA = -55oC to +125oC (M82C84A)
SYMBOL
PARAMETER
MIN
MAX
UNITS
TEST CONDITIONS
VIH Logical One Input Voltage
2.0 -
2.2
V C82C84A, I82C84
V M82C84A, Notes 1, 2
VIL
VIHR
VILR
VT+ - VT-
Logical Zero Input Voltage
Reset Input High Voltage
Reset Input Low Voltage
Reset Input Hysteresis
VOH Logical One Output Current
VOL Logical Zero Output Voltage
II Input Leakage Current
-
VCC -0.8
-
0.2 VCC
VCC -0.4
-
-1.0
0.8
-
0.5
-
-
0.4
1.0
V Notes 1, 2, 3
V
V
-
V IOH = -4.0mA for CLK Output
IOH = -2.5mA for All Others
V IOL = +4.0mA for CLK Output
IOL = +2.5mA for All Others
A VIN = VCC or GND except ASYNC,
X1: (Note 4)
ICCOP Operating Power Supply Current
- 40 mA Crystal Frequency = 25MHz
Outputs Open, Note 5
NOTES:
1. F/C is a strap option and should be held either 0.8V or 2.2V. Does not apply to X1 or X2 pins.
2. Due to test equipment limitations related to noise, the actual tested value may differ from that specified, but the specified limit is
guaranteed.
3. CSYNC pin is tested with VIL 0.8V.
4. ASYNC pin includes an internal 17.5knominal pull-up resistor. For ASYNC input at GND, ASYNC input leakage current = 300A
nominal, X1 - crystal feedback input.
5. f = 25MHz may be tested using the extrapolated value based on measurements taken at f = 2MHz and f = 10MHz.
Capacitance TA = +25oC
SYMBOL
PARAMETER
CIN
COUT
Input Capacitance
Output Capacitance
TYPICAL
10
15
UNITS
pF
pF
TEST CONDITIONS
FREQ = 1MHz, all measurements are
referenced to device GND
7 FN2974.4
September 9, 2015

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CS82C84A

CMOS Clock Generator Driver

Intersil Corporation
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