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CS8415A 데이터시트 PDF




Cirrus Logic에서 제조한 전자 부품 CS8415A은 전자 산업 및 응용 분야에서
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부품번호 CS8415A 기능
기능 96 kHz DIGITAL AUDIO INTERFACE RECEIVER
제조업체 Cirrus Logic
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CS8415A 데이터시트, 핀배열, 회로
CS8415A
96 kHz Digital Audio Interface Receiver
Features
! Complete EIAJ CP1201, IEC-60958, AES3,
S/PDIF-compatible Receiver
! +5.0 V Analog Supply (VA+)
! +3.3 V or +5.0 V Digital Interface (VL+)
! 7:1 S/PDIF Input MUX
! Flexible 3-wire Serial Digital Output Port
! 8-kHz to 96-kHz Sample Frequency Range
! Low-jitter Clock Recovery
! Pin and Microcontroller Read Access to
Channel Status and User Data
! Microcontroller and Standalone Modes
! Differential Cable Receiver
! On-chip Channel Status and User Data Buffer
Memories
! Auto-detection of Compressed Audio Input
Streams
! Decodes CD Q Sub-Code
! OMCK System Clock Mode
General Description
The CS8415A is a monolithic CMOS device which re-
ceives and decodes one of 7 channels of audio data
according to the IEC60958, S/PDIF, EIAJ CP1201, or
AES3. The CS8415A has a serial digital audio output
port and comprehensive control ability through a 4-wire
microcontroller port. Channel status and user data are
assembled in block-sized buffers, making read access
easy.
A low-jitter clock recovery mechanism yields a very
clean recovered clock from the incoming AES3 stream.
Stand-alone operation allows systems with no micro-
controller to operate the CS8415A with dedicated
output pins for channel status data.
The CS8415A is available in a 28-pin TSSOP and SOIC
package in both Commerical (-10 to +70°C) and Indus-
trial grades (-40 to +85° C). The CDB8415A Customer
Demonstration board is also available for device evalu-
ation and implementation suggestions. Please refer to
page 2 for ordering information.
Target applications include A/V receivers, CD-R, DVD
receivers, multimedia speakers, digital mixing consoles,
effects processors, set-top boxes, and computer and
automotive audio systems.
VA+ AGND FILT RERR RMCK
VL+ DGND OMCK
RXN0
RXP6
RXP5
RXP4
RXP3
RXP2
RXP1
RXP0
Receiver
Clock & AES3
Data
S/PDIF
Recovery Decoder
7:1
MUX
Misc.
Control
C & U bit
Data
Buffer
Control
Port &
Registers
Serial
Audio
Output
H/S RST EMPH U
SDA/ SCL/ AD1/ AD0/ INT
CDOUT CCLK CDIN CS
OLRCK
OSCLK
SDOUT
http://www.cirrus.com
Copyright © Cirrus Logic, Inc. 2005
(All Rights Reserved)
AUGUST '05
DS470F4




CS8415A pdf, 반도체, 판매, 대치품
CS8415A
13. APPENDIX A: EXTERNAL AES3/SPDIF/IEC60958 RECEIVER COMPONENTS .......................... 35
13.1 AES3 Receiver External Components ........................................................................................ 35
13.2 Isolating Transformer Requirements .......................................................................................... 36
14. APPENDIX B: CHANNEL STATUS AND USER DATA BUFFER MANAGEMENT ........................ 37
14.1 AES3 Channel Status (C) Bit Management ................................................................................ 37
14.2 Accessing the E Buffer ............................................................................................................... 37
14.2.1 Reserving the First 5 Bytes in the E Buffer .................................................................... 38
14.2.2 Serial Copy Management System (SCMS) .................................................................... 38
14.2.3 Channel Status Data E Buffer Access ........................................................................... 38
14.2.3.1 One-Byte Mode .................................................................................................. 38
14.2.3.2 Two-Byte Mode .................................................................................................. 39
14.3 AES3 User (U) Bit Management ................................................................................................. 39
15. APPENDIX C: PLL FILTER ............................................................................................................... 40
15.1 General ....................................................................................................................................... 40
15.2 External Filter Components ........................................................................................................ 41
15.2.1 General .......................................................................................................................... 41
15.2.2 Capacitor Selection ........................................................................................................ 41
15.2.3 Circuit Board Layout ...................................................................................................... 41
15.3 Component Value Selection ....................................................................................................... 42
15.3.1 Identifying the Part Revision .......................................................................................... 42
15.3.2 External Components .................................................................................................... 42
15.3.3 Jitter Tolerance .............................................................................................................. 43
15.3.4 Jitter Attenuation ............................................................................................................ 44
16. REVISION HISTORY ........................................................................................................................ 45
4 DS470F4

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CS8415A 전자부품, 판매, 대치품
DIGITAL INPUT CHARACTERISTICS
CS8415A
Parameters
Input Leakage Current
Differential Input Voltage, RXP0 to RXN0
Symbol Min Typ Max Units
Iin
-
±1 ±10
µA
VTH - 200 - mV
DIGITAL INTERFACE SPECIFICATIONS
AGND = DGND = 0 V; all voltages with respect to 0 V.
Parameters
High-Level Output Voltage (IOH = -3.2 mA)
Low-Level Output Voltage (IOH = 3.2 mA)
High-Level Input Voltage, except RXn
Low-Level Input Voltage, except RXn
(Note 5)
Symbol
VOH
VOL
VIH
VIL
Min Max
(VL+) - 1.0
-
- 0.4
2.0 (VL+) + 0.3
-0.3 0.4/0.8
5. At 5.0 V mode, VIL = 0.8 V (Max), at 3.3 V mode, VIL =0.4 V (Max).
Units
V
V
V
V
SWITCHING CHARACTERISTICS
Inputs: Logic 0 = 0 V, Logic 1 = VL+; CL = 20 pF.
Parameter
RST pin Low Pulse Width
PLL Clock Recovery Sample Rate Range
RMCK output jitter
RMCK output duty cycle
Symbol
(Note 6)
Min
200
8.0
-
40
6. Cycle-to-cycle using 32 to 96 kHz external PLL filter components.
Typ Max Units
- - µs
- 108.0 kHz
200 - ps RMS
50 60
%
DS470F4
7

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