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PDF CS8416-IS Data sheet ( Hoja de datos )
| Número de pieza | CS8416-IS | |
| Descripción | 192 kHZ DIGITAL AUDIO INTERFACE RECEIVER | |
| Fabricantes | Cirrus Logic | |
| Logotipo |  |
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CS8416
192 kHz Digital Audio Interface Receiver
Features
Complete EIAJ CP1201, IEC-60958, AES3,
S/PDIF-Compatible Receiver
+3.3 V Analog Supply (VA)
+3.3 V Digital Supply (VD)
+3.3 V or +5.0 V Digital Interface Supply (VL)
8:2 S/PDIF Input MUX
AES/SPDIF Input Pins Selectable in Hardware
Mode
Three General Purpose Outputs (GPO) Allow
Signal Routing
Selectable Signal Routing to GPO Pins
S/PDIF-to-TX Inputs Selectable in Hardware
Mode
Flexible 3-wire Serial Digital Output Port
32 kHz to 192 kHz Sample Frequency Range
Low-Jitter Clock Recovery
Pin and Microcontroller Read Access to
Channel Status and User Data
SPI™ or I²C® Control Port Software Mode and
Stand-Alone Hardware Mode
Differential Cable Receiver
On-Chip Channel Status Data Buffer Memories
Auto-Detection of Compressed Audio Input
Streams
Decodes CD Q Sub-Code
OMCK System Clock Mode
See the General Description and Ordering Information
on page 2.
VA AGND FILT RMCK
VD VL DGND OMCK
RXN
RXP0
RXP1
RXP2
RXP3
RXP4
RXP5
RXP6
RXP7
Receiver
Clock & AES3
Data
S/PDIF
Recovery Decoder
8:2
MUX
TX Passthrough
Misc.
Control
Format
Detect
De-emphasis
Filter
C & U bit
Data Buffer
Control
Port &
Registers
Serial
Audio
Output
n:3
MUX
RST
SDA/ SCL/ AD1/ AD0/
CDOUT CCLK CDIN CS
OLRCK
OSCLK
SDOUT
GPO0
GPO1
AD2/GPO2
http://www.cirrus.com
Copyright © Cirrus Logic, Inc. 2007
(All Rights Reserved)
AUGUST '07
DS578F3
1 page  
CS8416
LIST OF FIGURES
Figure 1. Audio Port Master Mode Timing ................................................................................................... 9
Figure 2. Audio Port Slave Mode and Data Input Timing............................................................................. 9
Figure 3. SPI Mode Timing ........................................................................................................................ 10
Figure 4. I²C Mode Timing ......................................................................................................................... 11
Figure 5. Typical Connection Diagram - Software Mode ........................................................................... 20
Figure 6. Typical Connection Diagram - Hardware Mode .......................................................................... 21
Figure 7. Serial Audio Output Example Formats........................................................................................ 24
Figure 8. AES3 Data Format...................................................................................................................... 25
Figure 9. Receiver Input Structure ............................................................................................................. 27
Figure 10. C/U Data Outputs...................................................................................................................... 32
Figure 11. Control Port Timing in SPI Mode .............................................................................................. 33
Figure 12. Control Port Timing, I²C Slave Mode Write............................................................................... 34
Figure 13. Control Port Timing, I²C Slave Mode Read............................................................................... 34
Figure 14. De-Emphasis Filter Response .................................................................................................. 39
Figure 15. Hardware Mode Data Flow ....................................................................................................... 46
Figure 16. Professional Input Circuit .......................................................................................................... 49
Figure 17. Transformerless Professional Input Circuit ............................................................................... 49
Figure 18. Consumer Input Circuit ............................................................................................................. 50
Figure 19. S/PDIF MUX Input Circuit ......................................................................................................... 50
Figure 20. TTL/CMOS Input Circuit............................................................................................................ 50
Figure 21. Channel Status Data Buffer Structure....................................................................................... 52
Figure 22. Flowchart for Reading the E Buffer........................................................................................... 52
Figure 23. PLL Block Diagram ................................................................................................................... 53
Figure 24. Recommended Layout Example............................................................................................... 54
Figure 25. Jitter Attenuation Characteristics of PLL................................................................................... 55
LIST OF TABLES
Table 1. Typical Delays by Frequency Values ........................................................................................... 26
Table 2. Clock Switching Output Clock Rates............................................................................................ 28
Table 3. GPO Pin Configurations............................................................................................................... 29
Table 4. Hardware Mode Start-Up Pin Conditions ..................................................................................... 47
Table 5. Hardware Mode Serial Audio Format Select................................................................................ 48
Table 6. External PLL Component Values ................................................................................................. 54
DS578F3
5
5 Page 
CS8416
SWITCHING CHARACTERISTICS - CONTROL PORT- I²C FORMAT
(Inputs: Logic 0 = 0 V, Logic 1 = VL; CL = 20 pF)
Parameter
Symbol
Min
Max
SCL Clock Frequency
Bus Free Time Between Transmissions
Start Condition Hold Time (prior to first clock pulse)
Clock Low time
Clock High Time
Setup Time for Repeated Start Condition
SDA Hold Time from SCL Falling
(Note 15)
SDA Setup time to SCL Rising
Rise Time of SCL and SDA
Fall Time SCL and SDA
Setup Time for Stop Condition
fscl
tbuf
thdst
tlow
thigh
tsust
thdd
tsud
tr
tf
tsusp
-
4.7
4.0
4.7
4.0
4.7
10
250
-
-
4.7
100
-
-
-
-
-
-
-
1000
300
-
Unit
kHz
µs
µs
µs
µs
µs
ns
ns
ns
ns
µs
Notes:
15. Data must be held for sufficient time to bridge the 300 ns transition time of SCL.
Stop Start
Repeated
Start
SDA
SCL
t buf t hdst
t high
t hdst
tf
t low
t hdd
t sud
t sust
Figure 4. I²C Mode Timing
tr
Stop
t susp
DS578F3
11
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| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet CS8416-IS.PDF ] | |
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