Datasheet.kr   

CT1820 데이터시트 PDF




Aeroflex Circuit Technology에서 제조한 전자 부품 CT1820은 전자 산업 및 응용 분야에서
광범위하게 사용되는 반도체 소자입니다.


PDF 형식의 CT1820 자료 제공

부품번호 CT1820 기능
기능 CT1820 Data Terminal Bit Processor for MIL-STD-1553 A & B
제조업체 Aeroflex Circuit Technology
로고 Aeroflex Circuit Technology 로고


CT1820 데이터시트 를 다운로드하여 반도체의 전기적 특성과 매개변수에 대해 알아보세요.




전체 10 페이지수

미리보기를 사용할 수 없습니다

CT1820 데이터시트, 핀배열, 회로
CT1820
Data Terminal Bit Processor
for MIL-STD-1553 A & B
Features
• Performs Encoder, Decoder, Logic and Control functions of a Data Bus Terminal to
MIL-STD-1553 specifications, including Address, Mode Code and Broadcast Decoding and
Terminal Fail Safe
• Flexibility - all control lines accessible
• Parallel tri-state subsystem l/O bus compatible with both 16 bit and 8 bit systems
• Dual rank l/O registers for versatile subsystem tlmlng
• Operates from +5VDC @ 40mA typical (25mA CT1820)
• Self-contained oscillator and clock driver
• Look-ahead serial receive data output
• Self-test, on-line wraparound, plus off-line capability
1
General Description
FLEX LA
ISO
9001
CE R T I F I E D
The CT1555-3/CT1820 Bit Processor Unit (BPU) is an advanced Hybrid Microcircuit that provides the interface between a
MIL-STD-1553 Transceiver such as CT3231M or CT3232M, and the subsystem internal parallel data bus. The unit can be
employed as the mux bus interface for Remote Subsystems or Master Terminal Bus Controllers, thus providing a common
interface for all systems communicating over the bus.
The unit places no restrictions on Command, Response or polling operations as it transfers all Command, Status and Data
words from the bus to parallel output lines, together with error information, bus status and handshaking signals. It also
contains 5 Bit Address Recognition, Broadcast and Mode Code Decode, Terminal Fail Safe Signal and Self Test.
In the transmit mode, it accepts parallel data from the user and transmits Command, Status and Data words, under
subsystem control, to the data bus. Positive handshaking signals provide logic control synchronisation between the unit
and the subsystem for direct data flow.
The hybrid is completely compatible with all the electrical and functional spec requirements of MIL-STD-1553 A & B.
FIRST
RANK
REC’V
REG
DO - D7
FIRST
RANK
REC’V
REG
D8 - D15
SECOND
RANK
REC’V
REG
DO - D7
SECOND
RANK
REC’V
REG
D8 - D15
FIRST
RANK
XMT
REG
DO - D7
FIRST
RANK
XMT
REG
D8 - D15
SECOND
RANK
XMT
REG
DO - D7
SECOND
RANK
XMT
REG
D8 - D15
Vcc
+5V
GND
GND
1
11
34
CASE
20
36
32
{5 BIT
ADDRESS
12
8
9
10
13
SERIAL DATA OUT
RT ENABLE
(MSB) A4
A3
A2
A1
ADDRESS
DECODE
(LSB) A0
BROADCAST BROAD-
39 CAST
DECODE
MODE CODE MODE
40 CODE
DECODE
VALID WORD
14
COMM/DATA SYNC
16
DEC RST
33
TAKE DATA
37
DSC OUT
31
MANCHESTER
DECODER
&
CONTROL LOGIC
MANCHESTER
ENCODER
&
CONTROL LOGIC
OSC
&
CLOCK
DRIVER
Figure 1 – Functional Diagram
BUILT IN
TEST
SELECT
DATA IN
DATA IN
BIT SELECT
DATA OUT
DATA OUT
FAIL SAFE
TIMER
&
CONTROL
FAIL SAFE
SEND DATA
ESCOUT
SYNC SEL
ENC ENA
OUTPUT INH
MRST
+5V OSC / CLOCK POWER
XTAL
CLOCK OUT
CLOCK IN
21
22
19
25
26
15
27
28
24
23
35
38
30
29
18
17
eroflex Circuit Technology – Data Bus Modules For The Future © SCDCT1820 REV D 6/25/99




CT1820 pdf, 반도체, 판매, 대치품
Pin Name
No
33 DEC RST
34 GROUND
35 OUTPUT INH
36 SERIAL DATA OUT
37 TAKE DATA
38 MRST
39 BROADCAST*
40 MODE CODE*
41 D6
42 D7
43 DATA SELECT 2
44 D5
45 D0
46 D1
47 D2
48 D3
49 LATCH DATA 2
50 D4
51 LOAD DATA 2
52 LATCH DATA 1
53 LOAD DATA 1
54 D13
55 D14
56 D15
IIH
(µA)
20
20
60
40
CT1555-3
CT1820
CT1820-2
IIL IOH IOL IIH IIL IOH IOL
(µA) (µA) (mA (µA) (µA) (µA) (mA
IOL
(mA)
-0.4 20 -0.4
-0.4 20 -0.4
-400 1.6
-400 4.0
-360 2.4
-400 4.0
-1.2 20 -0.4
4.0
4.0
-300 1.6
-400 4.0
4.0
-600 2.4
-600 6.0
6.0
-0.4 -1000 2.4 20 -0.4 -1000 6.0 10.0
Description
A LOW on this input (for 1µs minimum) resets the decoder
to a condition ready for a new word, resets the COMM /
DATA SYNC output LOW, and resets the VALID WORD
output HIGH.
Logic and Power Return.
A LOW on this input holds output pins 25 and 26 LOW.
The received serial data in NRZ format is available at this
pin during LOW TAKE DATA.
A LOW on this output indicates data shifting during the
receive cycle.
A LOW on this input (for 1µs minimum) interrupts and
clears the transmit cycle, resets the FAIL SAFE, and also
performs the same functions as DEC RST.
A HIGH on this output indicates reception of a valid
COMMAND (or STATUS) word containing all ONES in the
address field.
A LOW on this output indicates reception of a valid
COMMAND (or STATUS) word containing all ONES or all
ZEROS in the sub-address field.
Part of 16 Bit TRI-STATE l/O
20 -0.4
20 -0.4
A LOW on this input applies the contents of the SECOND
RANK REC’V REG to the D0-D7 I/O pins.
40 -0.4 -1000 2.4 20 -0.4 -1000 6.0 10.0 Part of 16 Bit TRI-STATE l/O
LSB of 16BIT TRI-STATE I/O
Part of 16 Bit TRI-STATE l/O
Part of 16 Bit TRI-STATE l/O
Part of 16 Bit TRI-STATE l/O
20 -0.4
A HIGH on this input allows the l/O data on D0-D7 to
appear at the output of the FIRST RANK XMT REG. A
LOW on this input holds the register outputs in their last
state.
40 -0.4 -1000 2.4
-1000 6.0
Part of 16 Bit TRl-STATE l/O
60 -1.2
A LOW on this input loads the D0-D7 data into the
SECOND RANK XMT REG. A HIGH on this input then
locks out the data inputs to permit serial shifting.
20 -0.4
A HIGH on this input allows the l/O data on D8-D15 to
appear at the output of the FIRST RANK XMT REG. A
LOW on this input holds the register outputs in their last
state.
60 -1.2
20 -0.4
A LOW on this input loads the D8-D15 data into the
SECOND RANK XMT REG. A HIGH on this input then
locks out the data inputs to permit serial shifting.
40 -0.4 -1000 2.4
-1000 6.0 10.0 Part of 16 Bit TRl-STATE l/O.
OPTIONAL SERIAL INPUT.
Aeroflex Circuit Technology
4 SCDCT1820 REV D 6/25/99 Plainview NY (516) 694-6700

4페이지










CT1820 전자부품, 판매, 대치품
RECEIVE CYCLE OPERATION
DECODER SHIFT CLOCK (DSC) (see Figure 5)
operates at the data rate (1MHz). When the
DECODER recognises a valid sync and two valid
Manchester data bits x, a receive cycle is initiated.
The new sync is indicated at the COMMAND/DATA
SYNC (C/D SYNC) output and the TAKE DATA
output goes low y. The C/D sync output will remain
in its valid state until a new sync is detected on a
subsequent word or until DECODER RESET (DEC
RST) or MRST goes low. A low at DEC RST or
MRST causes C/D SYNC to go low.
TAKE DATA remains low for 16 DSC periods during
which time the 16 serial data bits appear at the
SERIAL DATA OUTPUT (SDO). This data is
simultaneously loaded into the first-rank receive
register. The low-to-high transition of TAKE DATA z
makes the new data available at the output of the
second-rank receive register. This data remains
available until the next low-to-high transitions of
TAKE DATA. It is not reset or cleared by any other
signals. This data is applied to the D0 to D15 I/O
bus by setting DATA SELECT lines low.
After all data has been loaded into the receive
registers, the data is checked for odd parity. A low
on VALID WORD (VW) output z, indicates
successful reception of a word without any
Manchester or parity errors. For consecutive word
receptions, VW will go high again in 3 to 3.5µs. In
the absence of succeeding valid syncs, VW will
return high in 20µs. A DEC RST (low) at any time
will reset VW high.
All decoded commands, including RT ENABLE
(address recognition), BROADCAST and MODE
CODE are enabled internally by VW and remain
valid only as long as VW is low.
For 8-BIT l/O subsystems (D0 tied to D8, through
D7 tied to D15), data may be extracted in 8 BIT
bytes by selectively activating DATA SELECT 1 and
DATA SEL.ECT 2.
For serial data systems, SERIAL DATA OUTPUT is
available at the DSC rate from y to z.
OSC
012345
16 17 18 19 0 1 2 3 4 5
16 17 18 19
DATA IN
DATA IN
½ SYNC ½ SYNC 15 14 13
½ SYNC ½ SYNC 15 14 13
2 1 0 P ½ SYNC ½ SYNC 15 14 13
2 1 0 P ½ SYNC ½ SYNC 15 14 13
210P
210P
TAKE DATA
C/D SYNC
FROM PREVIOUS WORD
VALID FOR CURRENT WORD
VALID FOR CURRENT WORD
SDO
UNDEFINED
15 4 3 2 1 0
UNDEFINED
15
4321
0
VW
FROM PREVIOUS WORD
DECODE COMMANDS
(see text)
SECOND-RANK REC’V
REGISTER CONTENT
NOT VALID
FROM PREVIOUS WORD
DATA SELECT
OPTIONAL–HIGH = TRISTATE HI-Z AT D0 TO D15
VALID
NEW DATA
NOT VALID
OPTIONAL–HIGH = TRISTATE HI-Z AT D0 TO D15
VALID
NEW DATA
12
34
Figure 5 – Receive Cycle Timing
Aeroflex Circuit Technology
7 SCDCT1820 REV D 6/25/99 Plainview NY (516) 694-6700

7페이지


구       성 총 10 페이지수
다운로드[ CT1820.PDF 데이터시트 ]

당사 플랫폼은 키워드, 제품 이름 또는 부품 번호를 사용하여 검색할 수 있는

포괄적인 데이터시트를 제공합니다.


구매 문의
일반 IC 문의 : 샘플 및 소량 구매
-----------------------------------------------------------------------

IGBT, TR 모듈, SCR 및 다이오드 모듈을 포함한
광범위한 전력 반도체를 판매합니다.

전력 반도체 전문업체

상호 : 아이지 인터내셔날

사이트 방문 :     [ 홈페이지 ]     [ 블로그 1 ]     [ 블로그 2 ]



관련 데이터시트

부품번호상세설명 및 기능제조사
CT1820

CT1820 Data Terminal Bit Processor for MIL-STD-1553 A & B

Aeroflex Circuit Technology
Aeroflex Circuit Technology

DataSheet.kr       |      2020   |     연락처      |     링크모음      |      검색     |      사이트맵