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CT2554 데이터시트 PDF




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부품번호 CT2554 기능
기능 CT2553 / 2554 / 2555 / 2556 Advanced Integrated MUX (AIM) Hybrid FOR MIL-STD-1553
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CT2554 데이터시트, 핀배열, 회로
CT2553 / 2554 / 2555 / 2556
Advanced Integrated MUX (AIM) Hybrid
FOR MIL-STD-1553
Features
I Second Source Compatible to the BUS-61553
I Complete Integrated MUX Including:
Low Power Dual Transceiver
BC/RTU/MT Protocol
8K x 16 Shared Ram
Interrupt Logic
I Compatible with MIL-STD- 1750 and other Standard CPUs
I DIP or Flatpack Hybrid
I Minimizes CPU Overhead
I Provides Memory Mapped 1553 Interface
I On-Line & Off-Line Self-Test
I PCs Development Tools Available
I SEAFAC Tested
I MIL-PRF-38534 compliant circuits available
I DESC SMD #5962–88692 Pending
I Packaging – Hermetic Metal
78 Pin, 2.1" x 1.87" x .25" Plug-In type package
82 Lead, 2.2" x 1.61" x .18" Flat package
CIRCUIT TECHNOLOGY
www.aeroflex.com
FLEX LA
ISO
9001
CE R T I F I E D
General Description
Aeroflex’s CT2553 Advanced Integrated Mux (AIM) Hybrid is a complete MIL-STD-1553 Bus
Controller (BC), Remote Terminal Unit (RTU), and Bus Monitor (MT) device. Packaged in a single
78 pin DIP package, the CT2553 contains dual low-power transceivers, complete BC/RTU/MT
protocol logic, a MIL-STD-1553-to-host interface unit and an 8K x 16 RAM.
Using an industry standard dual transceiver and standard status and control signals, the CT2553
simplifies system integration at both the MIL-STD-1553 and host processor interface levels.
All 1553 operations are controlled through the CPU access to the shared 8K x 16 RAM. To ensure
maximum design flexibility, memory control lines are provided for attaching external RAM to the
CT2553 Address and Data Buses and for disabling internal memory; the total combined memory
space can be expanded to 64K x16. All 1553 transfers are entirely memory-mapped; thus the CPU
interface requires minimal hardware and/or software support.
The CT2553 operates over the full military -55°C to +125°C temperature range. Available screened
to MIL-STD883, the CT2553 is ideal for demanding military and industrial microprocessor to 1553
interface applications. See "Ordering Information" (last sheet) for CT2554, CT2555 & CT2556.
eroflex Circuit Technology – Data Bus Modules For The Future © SCDCT2553 REV B 8/6/99




CT2554 pdf, 반도체, 판매, 대치품
INTERFACING
The CT2553 is compatible with most common
microprocessors including, but not limited to, the
Motorola 680 x 0, the Intel 808x, Zilog Z800x and
MIL-STD-1750 processors.
Interfacing the CT2553 to the MIL-STD-1553
Data Bus requires two Q1553-2 pulse
transformers and an external 16 MHz clock (See
Figure 2). Tri-state buffers are used to isolate the
CPU's data and address lines.
External RAM can be used instead of or in
conjunction with the CT2553's internal 8K x 16
bits. The external RAM used by the CT2553 can
be any standard static memory with an access
time of < 55ns. The external RAM can be
expanded to 64K x 16.
Two control signals, MEMENA-IN (pin 69) and
MEMENMA-OUT (pin 31) are provided in
addition to the standard memory I/O signals for
internal/external memory access control (See
Figures 3-5. MEMEN-OUT and MEMEN-IN
should be tied together for Internal Memory Only
configuration. Memory CS signals can be
generated for configurations using external
memory.
MEMORY MANAGEMENT
Memory can be configured to support two AREAs
(A and B), each with an independent sequential
stack and pointers for manipulating 1553
message and control data. The CPU can access
the shared RAM while 1553 message transfers
are taking place. Arbitration of the RAM is
automatically implemented in a manner
transparent to the subsystem (See Figures
28-31). Variable Length DATA BLOCKS are also
stored in the shared RAM and can be addressed
by setting pointers residing in Area A, Area B or
both.
For BC/RTU operation, each area contains a
Descriptor Stack and Stack Pointer (See Figures
6 and 7). BC operation further maintains a
Message Count for each area (number of 1553
messages per frame). RTU operation maintains a
data block address Look-Up Table for each area.
MT operation utilizes a single Stack Pointer to
indicate the starting address for storage of
received words and associated identification
Words.
CURRENT AREA ASSIGNMENT/SWAPPING.
Current area status (currently available to the
1553 terminal) is Software programmable by the
host; the unassigned area automatically assumes
non-current area status. Both areas are always
addressable by the host. Swapping of the Current
Area can be done following message transfers for
user operations such as exception handling or
multiple buffering of 1553 data.
The host selects the Current Area by writing to
the CT2553’s Configuration Register with bit 13
set to the appropriate logic level (0 for area A or 1
for area B). Internal circuitry ensures that the
swapping of Current Area Status does not occur
during an ongoing message transfer (See
Configuration Register).
DESCRIPTOR STACK (BC/RTU). The
DESCRIPTOR STACK (DS) is divided into 64
entries. Each stack entry contains four words
which refer to one 1553 message. The Block
Status Word (BSW) indicates the physical bus on
which the message was received (RTU mode),
reports whether or not an error was detected
during message transfer and indicates message
completion (See Figure 8).
The user-supplied Time Tag word is loaded at the
start of a message transfer and is updated at the
end of the transfer (See Time Tagging).
Aeroflex Circuit Technology
4 SCDCT2553 REV B 8/6/99 Plainview NY (516) 694-6700

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CT2554 전자부품, 판매, 대치품
CONFIGURATION
REGISTER
15 13
0
STACK
POINTERS
*
CURRENT
AREA B/A
MESSAGE
COUNTER
*
DESCRIPTOR **
STACKS
BLOCK STATUS WORD
TIME TAG WORD
RESERVED
MESSAGE
BLOCK ADDR
DATA **
BLOCKS
DATA BLOCK
DATA BLOCK
* Note:
STACK POINTERS and MESSAGE COUNTERS are switched via the
CONFIGURATION REGISTER under external CPU control.
** Note:
DESCRIPTOR STACKS and DATA BLOCKS have 256 word boundries which
should be observed.
Figure 6 – Use of Descriptor Stack – BC Mode
CONFIGURATION
REGISTER
15 13
0
STACK
POINTERS
*
DESCRIPTOR **
STACKS
LOOK-UP TABLE
(DATA BLOCK ADDR)
*
DATA **
BLOCKS
CURRENT
AREA B/A
BLOCK STATUS WORD
TIME TAG WORD
RESERVED
RECEIVED COMMAND
WORD
LOOK-UP
TABLE ADDR
DATA BLOCK
DATA BLOCK
* Note:
STACK POINTERS and LOOK-UP TABLE are switched via the
CONFIGURATION REGISTER under external CPU control.
** Note:
DESCRIPTOR STACKS and DATA BLOCKS have 256 word boundries which
should be observed.
Aeroflex Circuit Technology
Figure 7 – Use of Descriptor Stack – RTU Mode
7 SCDCT2553 REV B 8/6/99 Plainview NY (516) 694-6700

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