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AT17C512 데이터시트 PDF




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부품번호 AT17C512 기능
기능 FPGA Configuration E2PROM Memory
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AT17C512 데이터시트, 핀배열, 회로
Features
E2 Programmable 524,288 x 1 and 1,048,576 x 1 bit Serial Memories Designed To Store
Configuration Programs For Field Programmable Gate Arrays (FPGA)
Simple Interface to SRAM FPGAs
Compatible With Atmel AT6000, AT40K FPGAs, Altera EPF8K, EPF10K,
EPF6K FPGAs, ORCA FPGAs, Xilinx XC3000, XC4000, XC5200 FPGAs, Motorola
MPA1000 FPGAs
Cascadable To Support Additional Configurations or Future Higher-density Arrays
Low-power CMOS EEPROM Process
Programmable Reset Polarity
Available In PLCC Package (Pin Compatable across Product Family)
In-System Programmable Via 2-Wire Bus
Emulation of 24CXX Serial EPROMs
Available in 3.3V ± 10% LV and 5V Versions
System Friendly READY Pin
Description
The AT17C512/010 and AT17LV512/010 (high-density AT17 Series) FPGA Configu-
ration EEPROMs (Configurators) provide an easy-to-use, cost-effective configuration
memory for Field Programmable Gate Arrays. The high-density AT17 Series is pack-
aged in the popular 20-pin PLCC. The high-density AT17 Series family uses a simple
serial-access procedure to configure one or more FPGA devices. The high-density
AT17 Series organization supplies enough memory to configure one or multiple
smaller FPGAs. The user can select the polarity of the reset function by programming
one EEPROM byte. The devices also support a write protection mode and a system
friendly READY pin, which signifies a “good” power level to the device and can be
used to ensure reliable system power-up.
The high-density AT17 Series can be programmed with industry-standard program-
mers, and the Atmel ATDH2200 Programming board.
FPGA
Configuration
E2PROM
Memory
512K and 1M
AT17C512
AT17LV512
AT17C010
AT17LV010
Pin Configurations
20-Pin PLCC
D
AV
N T NCN
CACCC
3 2 1 20 19
CLK 4
18 NC
WP1 5
17 SER_EN
RESET/OE 6
16 NC
WP2 7
1 5 READY
CE 8
14 CEO
9 10 11 12 13
NGNNN
CNCCC
D
Rev. 0944A-A–12/97
1




AT17C512 pdf, 반도체, 판매, 대치품
FPGA Master Serial Mode Summary
The I/O and logic functions of the FPGA and their associ-
ated interconnections are established by a configuration
program. The program is loaded either automatically upon
power up, or on command, depending on the state of the
three FPGA mode pins. In Master Mode, the FPGA auto-
matically loads the configuration program from an external
memory. The Serial Configuration EEPROM has been
designed for compatibility with the Master Serial Mode.
Cascading Serial Configuration
EEPROMs
For multiple FPGAs configured as a daisy-chain, or for
future FPGAs requiring larger configuration memories, cas-
caded Configurators provide additional memory.
As the last bit from the first Configurator is read, the clock
signal to the Configurator asserts its CEO output Low and
disables its DATA line. The second Configurator recog-
nizes the Low level on its CE input and enables its DATA
output.
Figure 1. Condition 1 Connection
After configuration is complete, the address counters of all
cascaded Configurators are reset if the reset signal drives
the RESET/OE on each Configurator to its active (High)
level.
If the address counters are not to be reset upon comple-
tion, then the RESET/OE inputs can be tied to ground. For
more details, please reference the AT17C Series Program-
ming Guide.
Programming Mode
The programming mode is entered by bringing SER_EN
Low. In this mode the chip can be programmed by the 2-
wire interface. The programming is done at VCC supply
only. Programming super voltages are generated inside the
chip. See the Programming Specification for Atmel's Con-
figuration Memories Application Note for further informa-
tion. The AT17C Series parts are read/write at 5V nominal.
The AT17LV parts are read/write at 3.3V nominal.
AT17C/LVXXX Reset Polarity
The AT17C/LVXXX lets the user choose the reset polarity
as either RESET/OE or RESET/OE.
Standby Mode
The AT17C/LVXXX enters a low-power standby mode
whenever CE is asserted High. In this mode, the Configura-
tor consumes less than 0.5mA at 5.0 volts. The output
remains in a high impedance state regardless of the state
of the OE input.
Operating Conditions
Symbol Description
Commercial
VCC Industrial
Military
Supply voltage relative to GND
-0°C to +70°C
Supply voltage relative to GND
-40°C to +85°C
Supply voltage relative to GND
-55°C to +125°C
AT17CXXX
Min/Max
4.75 / 5.25
4.5 / 5.5
4.5 / 5.5
AT17LVXXX
Min/Max
3.0 / 3.6
3.0 / 3.6
3.0 / 3.6
Units
V
V
V
4 AT17C/LV512/010

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AT17C512 전자부품, 판매, 대치품
AT17C/LV512/010
.
AC Characteristics for AT17C512/010
VCC = 5V ± 5% Commercial / VCC = 5V ± 10% Ind./Mil
Symbol
TOE(2)
TCE(2)
TCAC(2)
TOH(2)
TDF(3)
TLC
THC
TSCE
THCE
THOE
FMAX
VRDY
Description
OE to Data Delay
CE to Data Delay
CLK to Data Delay
Data Hold From CE, OE, or CLK
CE or OE to Data Float Delay
CLK Low Time
CLK High Time
CE Setup Time to CLK (to guarantee proper counting)
CE Hold Time to CLK (to guarantee proper counting)
OE High Time (Guarantees Counter Is Reset)
MAX Input Clock Frequency
Ready Pin Open Collector Voltage
Commercial/Industrial
Min Max
30
45
50
0
50
20
20
20
0
20
15
1.2 2.2
Military
Min Max
35
45
50
0
50
20
20
25
0
20
15
1.2 2.2
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
MHz
V
AC Characteristics for AT17C512/010 When Cascading
VCC = 5V± 5% Commercial / VCC = 5V ± 10% Ind./Mil.
Commercial/Industrial
Military
Symbol
Description
Min Max Min Max
TCDF (3)
CLK to Data Float Delay
TOCK(2)
CLK to CEO Delay
TOCE(2)
CE to CEO Delay
TOOE(2)
RESET/OE to CEO Delay
Notes: 1. Preliminary specifications for military operating range only.
50
35
35
30
50
40
35
30
2. AC test load = 50 pF.
3. Float delays are measured with 5 pF AC loads. Transition is measured ± 200 mV from steady state active levels.
Units
ns
ns
ns
ns
7

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