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AT17C65A 데이터시트 PDF




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부품번호 AT17C65A 기능
기능 FPGA Configuration EEPROM
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AT17C65A 데이터시트, 핀배열, 회로
Features
EE Programmable 65,536 x 1, 131,072 x 1 and 262,144 x 1 bit Serial Memories Designed
to Store Configuration Programs for Programmable Gate Arrays
Simple Interface to SRAM FPGAs Requires Only One User I/O Pin
Able to Configure with EPF6000 and EPF8000, Flex 10K FPGAs
Cascadable To Support Additional Configurations or Future Higher-Density Arrays
(17C128/256 only)
Low-Power CMOS EEPROM Process
Programmable Reset Polarity
Available in Industry-Standard Pin-Compatible PLCC Package
In-System Programmable via 2-Wire Bus
Emulation of 24CXX Serial EEPROMs
Available in 3.3V and 5V Versions
Description
The AT17C65/128/256A and AT17LV65/128/256A (AT17A Series) FPGA Configura-
tion EEPROMS (Configurator) provide an easy-to-use, cost-effective configuration
memory for Field Programmable Gate Arrays. The AT17A Series is packaged in the
popular 20-pin PLCC. The AT17A Series family uses a simple serial-access provides
to configure one or more FPGA devices. The AT17A Series organization supplies
enough memory to configure one or multiple smaller FPGAs. Using a special feature
of the AT17A Series, the user can select the polarity of the reset function by program-
ming a special EEPROM bit.
The AT17A Series is pin compatible with the industry standard configurator, and can
be programmed with industry standard programmers.
Pin Configurations
20-Pin PLCC
FPGA
Configuration
EEPROM
65K, 128K and 256K
AT17CxxxA
AT17LVxxxA
CLK (DCLK)
NC
NC
NC
RESET/OE (RESET/OE)
4
5
6
7
8
18 SER_EN
17 NC
16 NC
15 NC
14 NC
Rev. 0996A–07/98
1




AT17C65A pdf, 반도체, 판매, 대치품
FPGA Master Serial Mode Summary
The I/O and logic functions of the FPGA and their associ-
ated interconnections are established by a configuration
program. The program is loaded either automatically upon
power up, or on command, depending on the state of the
three FPGA mode pins. In Master Mode, the FPGA auto-
matically loads the configuration program from an external
memory. The Serial Configuration EEPROM has been
designed for compatibility with the Master Serial Mode.
Cascading Serial Configuration
EEPROMs (AT17C/LV256A)
For multiple FPGAs configured as a daisy-chain, or for
future FPGAs requiring larger configuration memories, cas-
caded Configurators provide additional memory
(17C/LV128/256A only).
After the last bit from the first Configurator is read, the next
clock signal to the Configurator asserts its CEO output Low
and disables its DATA line. The second Configurator rec-
ognizes the low level on its CE input and enables its DATA
output.
Figure 1. Condition 1 Connection
M2
M1
M0
FPGA
D0
CCLK
CS
CON
FLEX DEVICE
REBOOT
FLEX 10K, FLEX 16K
(CLK REQUIRED)
SERIAL
EEPROM
DATA
CLK
VCC
CE SER_EN
RESET/OE
AT17CXX
After configuration is complete, the address counters of all
cascaded Configurators are reset if the reset signal drives
the RESET/OE on each Configurator Active.
If the address counters are not to be reset upon comple-
tion, then the RESET/OE inputs can be tied to ground. For
more details, please reference the AT17C Series Program-
ming Guide
Programming Mode
The programming mode is entered by bringing SER_EN
low. In this mode the chip can be programmed by the 2-
wire interface. The programming is done at VCC supply
only. Programming super voltages are generated inside the
chip. See the Programming Specification for Atmel’s Con-
figuration Memories Application Note for further informa-
tion. The AT17C Series parts are read/write at 5V nominal.
The AT17LV parts are read/write at 3.0V nominal.
AT17C/LVxxx Reset Polarity
The AT17C/LVxxxA lets the user choose the reset polarity
as either RESET/OE or RESET/OE.
Standby Mode
The AT17C/LVxxxA enters a low-power standby mode
whenever CE is asserted high. In this mode, the Configura-
tor consumes less than 1.0 mA of current. The output
remains in a high-impedance state regardless of the state
of the OE input.
Operating Conditions
Symbol
VCC
Description
Commercial
Industrial
Military
Supply voltage relative to GND
-0°C to +70°C
Supply voltage relative to GND
-40°C to +85C°
Supply voltage relative to GND
-55°C to +125C
AT17Cxxx
Min/Max
4.75/5.25
AT17LVxxx
Min/Max
3.0/3.6
Units
V
4.5/5.5
3.0/3.6
V
4.5/5.5
3.0/3.6
V
4 AT17A Series

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AT17C65A 전자부품, 판매, 대치품
AT17A Series
.
AC Characteristics for AT17C256A
VCC = 5V ± 5% Commercial / VCC = 5V ± 10% Ind./Mil
Commercial
Industrial/Military
Symbol
tOE(2)
tCE(2)
tCAC(2)
tOH(2)
tDF(3)
tLC
tHC
tSCE
tHCE
tHOE
FMAX
Description
OE to Data Delay
CE to Data Delay
CLK to Data Delay
Data Hold From CE, OE, or CLK
CE or OE to Data Float Delay
CLK Low Time
CLK High Time
CE Setup Time to CLK (to guarantee proper counting)
CE Hold Time to CLk (to guarantee proper counting)
OE High Time (guarantees counter is reset)
MAX Input Clock Frequency
Min Max Min Max
25 25
45 45
50 55
00
50 50
20 20
20 20
35 40
00
20 20
12.5 12.5
.
AC Characteristics for AT17C256A When Cascading
VCC = 5V± 5% Commercial / VCC = 5V ± 10% Ind./Mil
Commercial
Industrial/Military
Symbol Description
Min Max Min Max
tCDF(3)
CLK to Data Float Delay
tOCK(2)
CLK to CEO Delay
tOCE(2)
CE to CEO Delay
tOOE(2)
RESET/OE to CEO Delay
Notes: 1. Preliminary specifications for military operating range only.
50 50
35 40
35 35
30 35
2. AC test load = 50 pf.
3. Float delays are measured with 5 pF AC loads. Transition is measured ±200 mV from steady-state active levels.
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
MHz
Units
ns
ns
ns
ns
7

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