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PDF AT17LV65 Data sheet ( Hoja de datos )
| Número de pieza | AT17LV65 | |
| Descripción | FPGA Configuration EEPROM Memory | |
| Fabricantes | ATMEL Corporation | |
| Logotipo |  |
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Note 1.
AT17LV65 and AT17LV128
are Not Recommended for
New Designs (NRND) and
are Replaced by AT17LV256.
AT17LV65(1), AT17LV128(1), AT17LV256,
AT17LV512, AT17LV010, AT17LV002, AT17LV040
FPGA Configuration EEPROM Memory
3.3V and 5.0V System Support
Features
DATASHEET
EE Programmable Serial Memories Designed to Store Configuration Programs
for Field Programmable Gate Arrays (FPGAs)
̶ 65,536 x 1-bit(1)
̶ 524,288 x 1-bit
̶ 2,097,152 x 1-bit
̶ 131,072 x 1-bit(1)
̶ 1,048,576 x 1-bit
̶ 4,194,304 x 1-bit
̶ 262,144 x 1-bit
Supports both 3.3V and 5.0V Operating Voltage Applications
In-System Programmable (ISP) via 2-wire Bus
Simple Interface to SRAM FPGAs
Compatible with the Atmel® AT6000, AT40K and AT94K Devices, Altera®
FLEX®, APEX™ Devices, ORCA®, Xilinx® XC3000, XC4000, XC5200,
Spartan®, Virtex® FPGAs
Cascadable Read-back to Support Additional Configurations or Higher-density
Arrays
Very Low-power CMOS EEPROM Process
Programmable Reset Polarity
Available in 6mm x 6mm x 1mm 8-lead LAP (Pin-compatible with 8-lead SOIC
Package), 8-lead PDIP, 8-lead SOIC, 20-lead PLCC, 20-lead SOIC and
44-lead TQFP Packages
Emulation of the Atmel AT24CXXX Serial EEPROMs
Low-power Standby Mode
High-reliability
̶ Endurance: 100,000 Write Cycles
̶ Data Retention: 90 Years for Industrial Parts (at 85C)
Green (Pb/Halide-free/RoHS Compliant) Package Options Available
Description
The AT17LV FPGA Configuration EEPROMs (Configurators) provide an easy-to-
use, cost-effective configuration memory solution for Field Programmable Gate
Arrays. The AT17LV devices are packaged in the 8-lead LAP, 8-lead PDIP, 8-lead
SOIC, 20-lead PLCC, 20-lead SOIC and 44-lead TQFP options(Table 1). The
AT17LV Configurators use a simple serial-access procedure to configure one or
more FPGA devices. The user can select the polarity of the reset function during
programming. These devices also support a write protection mechanism within its
programming mode.
Atmel-2321J-FPGA-AT17LV65-128-256-512-010-002-040-Datasheet_102014
1 page  
Figure 1-1. Pinouts(1)
8-lead LAP
(Top View)
8-lead JEDEC SOIC
(Top View)
8-lead PDIP
(Top View)
DATA
CLK
(WP(2)) RESET/OE
CE
1
2
3
4
8 VCC
DATA
7 SER_EN
CLK
6 CEO (A2) (WP(2)) RESET/OE
5 GND
CE
1
2
3
4
8 VCC
DATA 1
7 SER_EN
6 CEO (A2)
CLK 2
5 GND
(WP(2)) RESET/OE 3
CE 4
8 VCC
7 SER_EN
6 CEO (A2)
5 GND
20-lead PLCC
(Top View)
44-lead TQFP
(Top View)
AT17LV002 Only
CLK
(WP1(3)) NC
(WP1(2)) RESET/OE
(WP2(3)) NC
CE
4
5
6
7
8
18 NC
17 SER_EN
16 NC
15 NC (READY(3))
14 CEO(4) (A2)
NC
NC
NC
NC
NC
NC
(WP1(1)) NC
NC
NC
NC
NC
1
2
3
4
5
6
7
8
9
10
11
33 NC
32 NC
31 NC
30 NC
29 NC
28 NC
27 NC
26 NC
25 NC
24 NC
23 READY
20-lead SOIC
(Top View)
AT17LV65/128/256 Only(5)
NC
DATA
NC
CLK
NC
RESET/OE
NC
CE
NC
GND
1
2
3
4
5
6
7
8
9
10
20 VCC
19 NC
18 NC
17 SER_EN
16 NC
15 NC
14 CEO (A2)
13 NC
12 NC
11 NC
DATA
NC
CLK
NC
NC
NC
NC
RESET/OE
NC
CE
20-lead SOIC
(Top View)
AT17LV002 Only
1 20
2 19
3 18
4 17
5 16
6 15
7 14
8 13
9 12
10 11
VCC
NC
SER_EN
NC
NC
NC
NC
CEO(4)
NC
GND
Notes:
1. Drawings are not to scale.
2. This pin is only available on the AT17LV65 (NRND), AT17LV128 (NRND), and AT17LV256.
3. This pin is only available on the AT17LV512/010/002.
4. This pin is not available on the AT17LV65 (NRND).
5. The AT17LV65 and AT17LV128 are not recommended for new designs.
AT17LV65/128/256/512/010/002/040 [DATASHEET]
Atmel-2321J-FPGA-AT17LV65-128-256-512-010-002-040-Datasheet_102014
5
5 Page 
Table 10-5. AC Characteristics when Cascading for VCC = 3.3V ± 10%
AT17LV65/128/256(3)
Symbol Description
Min Max
TCDF(2)
TOCK(1)
TOCE(1)
TOOE(1)
FMAX
CLK to Data Float Delay
CLK to CEO Delay
CE to CEO Delay
RESET/OE to CEO Delay
Maximum Clock Frequency
60
60
60
45
8
AT17LV512/010/002/040
Min Max
50
55
40
35
10
Units
ns
ns
ns
ns
MHz
Notes: 1. AC test lead = 50pF.
2. Float delays are measured with 5pF AC loads. Transition is measured ± 200mV from steady-state active levels.
3. The AT17LV65 and AT17LV128 are not recommended for new designs.
Table 10-6. AC Characteristics for VCC = 5V ± 10%
Symbol
TOE(1)
TCE(1)
TCAC(1)
TOH
TDF(2)
TLC
THC
TSCE
THCE
THOE
FMAX
Description
OE to Data Delay
CE to Data Delay
CLK to Data Delay
Data Hold from CE, OE, or CLK
CE or OE to Data Float Delay
CLK Low Time
CLK High Time
CE Setup Time to CLK
(To Guarantee Proper Counting)
CE Hold Time from CLK
(To Guarantee Proper Counting)
OE High Time
(Guarantees Counter is Reset)
Maximum Clock Frequency
AT17LV65/128/256(3)
Min Max
35
45
55
0
50
20
20
40
0
20
12.5
AT17LV512/010/002/040
Min Max
35
45
50
0
50
20
20
Units
ns
ns
ns
ns
ns
ns
ns
25 ns
0 ns
20 ns
15 MHz
Notes: 1. AC test lead = 50pF.
2. Float delays are measured with 5pF AC loads. Transition is measured ± 200mV from steady-state active levels.
3. The AT17LV65 and AT17LV128 are not recommended for new designs.
AT17LV65/128/256/512/010/002/040 [DATASHEET]
Atmel-2321J-FPGA-AT17LV65-128-256-512-010-002-040-Datasheet_102014
11
11 Page | ||
| Páginas | Total 23 Páginas | |
| PDF Descargar | [ Datasheet AT17LV65.PDF ] | |
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