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PDF AT17LV65A Data sheet ( Hoja de datos )
| Número de pieza | AT17LV65A | |
| Descripción | FPGA Configuration EEPROM Memory | |
| Fabricantes | ATMEL Corporation | |
| Logotipo |  |
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Note 1.
AT17LV65A, AT17LV128A,
and AT17LV256A are
Not Recommended for New
Designs (NRND) and are
Replaced by AT17LV512A.
AT17LV65A(1), AT17LV128A(1), AT17LV256A(1)
AT17LV512A, AT17LV010A, AT17LV002A
FPGA Configuration EEPROM Memory
3.3V and 5V System Support
Features
DATASHEET
EE Programmable Serial Memories Designed to Store Configuration Programs for
Altera® FLEX® and APEX™ Field Programmable Gate Arrays (FPGA)
̶ 65,536 x 1-bit(1)
̶ 262,144 x 1-bit(1)
̶ 1,048,576 x 1-bit
̶ 131,072 x 1-bit(1)
̶ 524,288 x 1-bit
̶ 2,097,152 x 1-bit
Supports both 3.3V and 5.0V Operating Voltage Applications
In-System Programmable (ISP) via 2-wire Bus
Simple Interface to SRAM FPGAs
Compatible with the Atmel® AT6000, AT40K and AT94K Devices, Altera FLEX,
APEX Devices, ORCA® FPGAs, Xilinx® XC3000, XC4000, XC5200, Spartan®,
Virtex™ FPGAs, Motorola MPA1000 FPGAs
Cascadable Read-back to Support Additional Configurations or Higher-density Arrays
Very Low-power CMOS EEPROM Process
Programmable Reset Polarity
8-lead PDIP and 20-lead PLCC Packages (Pin-compatible Across Product Family)
Emulation of the Atmel AT24C Serial EEPROMs
Low-power Standby Mode
High-reliability
̶ Endurance: 100,000 Write Cycles
̶ Data Retention: 90 Years for Industrial Parts (at 85C)
Green (Pb/Halide-free/RoHS Compliant) Package Options Available
Description
The Atmel® AT17LVxxxA FPGA configuration EEPROMs (Configurators) provide an
easy-to-use, cost-effective configuration memory solution for FPGAs. The
AT17LVxxxA are packaged in 8-lead PDIP and 20-lead PLCC options. The
AT17LVxxxA configurator uses a simple serial-access procedure to configure one or
more FPGA devices. The user can select the polarity of the reset function by
programming four EEPROM bytes. These devices support a write protection
mechanism within its programming mode.
The AT17LVxxxA configurators can be programmed with industry-standard
programmers, the Atmel ATDH2200E Programming Kit, or the Atmel ATDH2225 ISP
Cable.
Table 1. AT17LVxxxA Packages
Package
8-lead PDIP
20-lead PLCC
AT17LV512A
Yes
Yes
AT17LV010A
Yes
Yes
AT17LV002A
–
Yes
Atmel-2322I-FPGA-AT17LV65A-128A-256A-512A-002A-Datasheet_102014
1 page  
3. Device Description
The control signals for the configuration EEPROM (nCS, RESET/OE and DCLK) interface directly with the
FPGA device control signals. All FPGA devices can control the entire configuration process and retrieve data
from the configuration EEPROM without requiring an external controller.
The configuration EEPROM’s RESET/OE and nCS pins control the tri-state buffer on the DATA output pin and
enable the address counter and the oscillator. When RESET/OE is driven Low, the configuration EEPROM
resets its address counter and tri-states its DATA pin. The nCS pin also controls the output of the AT17LVxxxA
configurator. If nCS is held High after the RESET/OE pulse, the counter is disabled and the DATA output pin is
tri-stated. When nCS is driven subsequently Low, the counter and the DATA output pin are enabled. When
RESET/OE is driven Low again, the address counter is reset and the DATA output pin is tri-stated, regardless of
the state of the nCS.
When the configurator has driven out all of its data and nCASC is driven Low, the device tri-states the DATA pin
to avoid contention with other configurators. Upon power-up, the address counter is automatically reset.
This is the default setting for the device. Since almost all FPGAs use RESET Low and OE High, this document
will describe RESET/OE.
4. FPGA Master Serial Mode Summary
The I/O and logic functions of any SRAM-based FPGA are established by a configuration program. The
program is loaded either automatically upon power-up, or on command, depending on the state of the FPGA
mode pins. In Master mode, the FPGA automatically loads the configuration program from an external memory.
The AT17LVxxxA Serial Configuration EEPROM has been designed for compatibility with the Master Serial
mode.
This document discusses the Altera FLEX FPGA device interfaces.
5. Control of Configuration
Most connections between the FPGA device and the AT17LVxxxA Serial EEPROM are simple and self-
explanatory.
The DATA output of the AT17LVxxxA configurator drives DIN of the FPGA devices.
The master FPGA DCLK output or external clock source drives the DCLK input of the AT17LVxxxA
configurator.
The nCASC output of any AT17LVxxxA configurator drives the nCS input of the next configurator in a
cascaded chain of EEPROMs.
SER_EN must be connected to VCC (except during ISP).
AT17LV65A/128A/256A/512A/002A [DATASHEET]
Atmel-2322I-FPGA-AT17LV65A-128A-256A-512A-002A-Datasheet_102014
5
5 Page 
10.5 Thermal Resistance Coefficients
Table 10-8. Thermal Resistance Coefficients
Package Type
8P3
Plastic Dual Inline
Package (PDIP)
20J
Plastic Leaded Chip
Carrier (PLCC)
JC [C/W]
JA [C/W](1)
JC [C/W]
JA [C/W](1)
AT17LV65A/128A/256A(2) AT17LV512A/010A
37
107
35 35
90 90
AT17LV002A
35
90
Notes: 1. Airflow = 0ft/min.
2. The AT17LV65A, AT17LV128A, and AT17LV256A are not recommended for new designs.
AT17LV65A/128A/256A/512A/002A [DATASHEET]
Atmel-2322I-FPGA-AT17LV65A-128A-256A-512A-002A-Datasheet_102014
11
11 Page | ||
| Páginas | Total 16 Páginas | |
| PDF Descargar | [ Datasheet AT17LV65A.PDF ] | |
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