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부품번호 | AT17N040 기능 |
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기능 | FPGA Configuration Memory | ||
제조업체 | ATMEL Corporation | ||
로고 | |||
전체 18 페이지수
Features
• EE Programmable 262,144 x 1-, 524,288 x 1-, 1,048,576 x 1-, 2,097,152 x 1-, and
4,194,304 x 1-bit Serial Memories Designed to Store Configuration Programs for Field
Programmable Gate Arrays (FPGAs)
• Available as a 3.3V (±10%) Commercial and Industrial Version
• Simple Interface to SRAM FPGAs
• Pin Compatible with Xilinx® XC17SXXXA and XC17SXXXXL PROMs
• Compatible with Xilinx Spartan®-II, Spartan-IIE and Spartan XL FPGAs in Master Serial
Mode
• Very Low-power CMOS EEPROM Process
• Available in 6 mm x 6 mm x 1 mm 8-lead LAP (Pin-compatible with 8-lead SOIC/VOIC
Packages), 8-lead PDIP, 8-lead SOIC, 20-lead SOIC and 44-lead TQFP Packages for a
Specific Density
• Low-power Standby Mode
• High-reliability
– Endurance: Minimum 10 Write Cycles
– Data Retention: 20 Years at 85°C
Description
The AT17N series FPGA Configuration EEPROM (Configurators) provide an easy-to-
use, cost-effective configuration memory for Field Programmable Gate Arrays. The
AT17N series device is packaged in the 8-lead LAP, 8-lead PDIP, 8-lead SOIC, 20-lead
SOIC and 44-lead TQFP, see Table 1. The AT17N series Configurators uses a simple
serial-access procedure to configure one or more FPGA devices.
The AT17N series configurators can be programmed with industry-standard program-
mers, Atmel’s ATDH2200E Programming Kit or Atmel’s ATDH2225 ISP Cable and
factory programming.
Table 1. AT17N Series Packages
Package
AT17N256
AT17N512/
AT17N010
AT17N002
AT17N040
8-lead LAP
–
Yes
Yes –
8-lead PDIP
8-lead SOIC
Yes Yes
–
Yes Use 8-lead LAP(1) Use 8-lead LAP(1)
–
–
20-lead SOIC
Yes
Yes
Yes –
44-lead TQFP
–
–
Yes Yes
Note:
1. The 8-lead LAP package has the same footprint as the 8-lead SOIC. Since an 8-
lead SOIC package is not available for the AT17N512/010/002 devices, it is possi-
ble to use an 8-lead LAP package instead.
FPGA
Configuration
Memory
AT17N256
AT17N512
AT17N010
AT17N002
AT17N040
3.3V
System Support
Rev. 3020A–CNFG–05/03
1
Block Diagram
SER_EN
POWER ON
RESET
Device Description
The control signals for the configuration EEPROM (CE, RESET/OE and CCLK) inter-
face directly with the FPGA device control signals. All FPGA devices can control the
entire configuration process and retrieve data from the configuration EEPROM without
requiring an external intelligent controller.
The configuration EEPROM RESET/OE and CE pins control the tri-state buffer on the
DATA output pin and enable the address counter. When RESET/OE is driven High, the
configuration EEPROM resets its address counter and tri-states its DATA pin. The CE
pin also controls the output of the AT17N series configurator. If CE is held High after the
RESET/OE reset pulse, the counter is disabled and the DATA output pin is tri-stated.
When OE is subsequently driven Low, the counter and the DATA output pin are
enabled. When RESET/OE is driven High again, the address counter is reset and the
DATA output pin is tri-stated, regardless of the state of CE. Upon power-up, the address
counter is automatically reset.
4 AT17N256/512/010/002/040
3020A–CNFG–04/10/03
4페이지 AT17N256/512/010/002/040
Absolute Maximum Ratings*
Operating Temperature.................................... -40°C to +85°C
Storage Temperature ..................................... -65 °C to +150°C
Voltage on Any Pin
with Respect to Ground ..............................-0.1V to VCC +0.5V
Supply Voltage (VCC) .......................................... 3.0V to +3.6V
Maximum Soldering Temp. (10 sec. @ 1/16 in.).............260°C
ESD (RZAP = 1.5K, CZAP = 100 pF)................................. 2000V
*NOTICE:
Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent dam-
age to the device. This is a stress rating only and
functional operation of the device at these or any
other conditions beyond those listed under oper-
ating conditions is not implied. Exposure to Abso-
lute Maximum Rating conditions for extended
periods of time may affect device reliability.
Operating Conditions
Symbol
VCC
Description
Commercial
Industrial
Supply voltage relative to GND
-0°C to +70°C
Supply voltage relative to GND
-40°C to +85°C
3.3V
Min Max
3.0 3.6
3.0 3.6
Units
V
V
3020A–CNFG–04/10/03
7
7페이지 | |||
구 성 | 총 18 페이지수 | ||
다운로드 | [ AT17N040.PDF 데이터시트 ] |
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구매 문의 | 일반 IC 문의 : 샘플 및 소량 구매 ----------------------------------------------------------------------- IGBT, TR 모듈, SCR 및 다이오드 모듈을 포함한 광범위한 전력 반도체를 판매합니다. 전력 반도체 전문업체 상호 : 아이지 인터내셔날 사이트 방문 : [ 홈페이지 ] [ 블로그 1 ] [ 블로그 2 ] |
부품번호 | 상세설명 및 기능 | 제조사 |
AT17N040 | FPGA Configuration Memory | ATMEL Corporation |
AT17N040-10TQC | FPGA Configuration Memory | ATMEL Corporation |
DataSheet.kr | 2020 | 연락처 | 링크모음 | 검색 | 사이트맵 |