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AT22LV10-20PC 데이터시트 PDF




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부품번호 AT22LV10-20PC 기능
기능 Low-Voltage UV Erasable Programmable Logic Device
제조업체 ATMEL Corporation
로고 ATMEL Corporation 로고


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AT22LV10-20PC 데이터시트, 핀배열, 회로
Features
Low Voltage Programmable Logic Device
– Wide Power Supply Range - 3.0V to 5.5V
– Ideal for Battery Powered Systems
High Speed Operation
– 20 ns max Propagation Delay at VCC = 3.0V
Commercial and Industrial Temperature Ranges
Familiar 22V10 Logic Architecture
Low Power 3-Volt CMOS Operation
Temp
ICC (mA)
AT22LV10L
Com./Ind.
4/5
AT22LV10
Com./Ind.
35 / 45
VCC = 3.6V
CMOS and TTL Compatible Inputs and Outputs
– 10 µA Leakage Maximum
Reprogrammable - Tested 100% for Programmability
High Reliability CMOS Technology
– 2000V ESD Protection
– 200 mA Latchup Immunity
Dual-In-Line and Surface Mount Packages
Logic Diagram
Low-Voltage UV
Erasable
Programmable
Logic Device
AT22LV10
AT22LV10L
Description
The AT22LV10 and AT22LV10L are low voltage compatible CMOS high performance
Programmable Logic Devices (PLDs). Speeds down to 20 ns and power dissipation
as low as 14.4 mW are offered. All speed ranges are specified over the 3.0V to 5.5V
range. All pins offer a low ±10 µA leakage.
(continued)
Pin Configurations
Pin Name
CLK/IN
IN
I/O
*
VCC
Function
Clock and Logic Input
Logic Inputs
Bidirectional Buffers
No Internal Connection
3.0V to 5.5V Supply
DIP/SOIC
PLCC
Rev. 0190C—05/98
1




AT22LV10-20PC pdf, 반도체, 판매, 대치품
AC Characteristics for the AT22LV10
Symbol
tPD
tEA
tER
tCF
tCO
tS
tH
tP
tW
FMAX
tAW
tAR
tAP
Parameter
Input or Feedback to Non-
Registered Output
Input to Output Enable
Input to Output Disable
Clock to Feedback
Clock to Output
Input or Feedback Setup Time
Hold Time
Clock Period
Clock Width
External Feedback 1/(tS+tCO)
Internal Feedback 1/(tS + tCF)
No Feedback 1/(tP)
Asynchronous Reset Width
Asynchronous Reset,
Synchronous Preset,
Recovery Time
Asynchronous Reset to
Registered Output Reset
AT22LV10-20
Min Typ Max
12 20
20
20
049
0 8 14
10 6
0
10
5
41.6
52.6
100.0
20 12
20 12
15 25
AT22LV10-25
Min Typ Max
15 25
15 25
15 25
059
0 10 17
12 7
0
12
6
34.5
47.6
83.3
25 15
25 15
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
MHz
MHz
MHz
ns
ns
18 28 ns
AC Waveforms(1)
Note: 1. Timing measurement reference is 1.5V. Input AC driving levels are 0.0V and 3.0V, unless otherwise specified.
4 AT22LV10(L)

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AT22LV10-20PC 전자부품, 판매, 대치품
AT22LV10(L)
Preload of Registered Outputs
The registers in the AT22LV10 and AT22LV10L are pro-
vided with circuitry to allow loading of each register asyn-
chronously with either a high or a low. This feature will
simplify testing since any state can be forced into the regis-
ters to control test sequencing. A VIH level on the I/O pin
will force the register high; a VIL will force it low, indepen-
dent of the polarity bit (C0) setting. The preload state is
entered by placing an 11.5V to 13V signal on pin 8 on
DIPs, and pin 10 on SMPs. When the clock pin is pulsed
high, the data on the I/O pins is placed into the ten regis-
ters.
Level forced on registered output
pin during preload cycle
VIH
VIL
Register state after
cycle
High
Low
Power-Up Reset
The registers in the AT22LV10 and AT22LV10L are
designed to reset during power up. At a point delayed
slightly from VCC crossing 2.5V, all registers will be reset
to the low state. The output state will depend on the polarity
of the output buffer.
This feature is critical for state machine initialization. How-
ever, due to the asynchronous nature of reset and the
uncertainty of how VCC actually rises in the system, the fol-
lowing conditions are required:
1. The VCC rise must be monotonis;
2. After reset occurs, all input and feedback setup
times must be met before driving the clock pin high,
and
3. The clock must remain stable during tPR.
Parameter
tPR
Description
Power-Up
Reset Time
Min
Typ Max Units
600 1000
ns
Pin Capacitance (f = 1 MHz, T = 25°C)(1)
Typ
Max
Units
Conditions
CIN 5 8 pF VIN = 0V
COUT
6 8 pF VOUT = 0V
Note: 1. Typical values for nominal supply voltage. This parameter is only sampled and is not 100% tested.
Erasure Characteristics
The entire fuse array of an AT22LV10 or AT22LV10L is
erased after exposure to ultraviolet light at a wavelength of
2537 Å. Complete erasure is assured after a minimum of
20 minutes exposure using 12,000 µW/cm2 intensity lamps
spaced one inch away from the chip. Minimum erase time
for lamps at other intensity ratings can be calculated from
the minimum integrated erasure dose of 15 Wsec/cm2. To
prevent unintentional erasure, an opaque label is recom-
mended to cover the clear window on any UV erasable
PLD which will be subjected to continuous fluorescent
indoor lighting or sunlight.
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관련 데이터시트

부품번호상세설명 및 기능제조사
AT22LV10-20PC

Low-Voltage UV Erasable Programmable Logic Device

ATMEL Corporation
ATMEL Corporation
AT22LV10-20PI

Low-Voltage UV Erasable Programmable Logic Device

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