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AT24C16 데이터시트 PDF




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부품번호 AT24C16 기능
기능 2-Wire Serial EEPROM
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AT24C16 데이터시트, 핀배열, 회로
Features
Low-Voltage and Standard-Voltage Operation
– 5.0 (VCC = 4.5V to 5.5V)
– 2.7 (VCC = 2.7V to 5.5V)
– 2.5 (VCC = 2.5V to 5.5V)
– 1.8 (VCC = 1.8V to 5.5V)
Internally Organized 128 x 8 (1K), 256 x 8 (2K), 512 x 8 (4K),
1024 x 8 (8K) or 2048 x 8 (16K)
2-Wire Serial Interface
Schmitt Trigger, Filtered Inputs for Noise Suppression
Bidirectional Data Transfer Protocol
100 kHz (1.8V, 2.5V, 2.7V) and 400 kHz (5V) Compatibility
Write Protect Pin for Hardware Data Protection
8-Byte Page (1K, 2K), 16-Byte Page (4K, 8K, 16K) Write Modes
Partial Page Writes Are Allowed
Self-Timed Write Cycle (10 ms max)
High Reliability
– Endurance: 1 Million Write Cycles
– Data Retention: 100 Years
– ESD Protection: >3000V
Automotive Grade and Extended Temperature Devices Available
8-Pin and 14-Pin JEDEC SOIC, 8-Pin PDIP, 8-Pin MSOP, and 8-Pin TSSOP Packages
Description
The AT24C01A/02/04/08/16 provides 1024/2048/4096/8192/16384 bits of serial elec-
trically erasable and programmable read only memory (EEPROM) organized as
128/256/512/1024/2048 words of 8 bits each. The device is optimized for use in many
industrial and commercial applications where low power and low voltage operation are
essential. The AT24C01A/02/04/08/16 is available in space saving 8-pin PDIP,
(AT24C01A/02/04/08/16), 8-Pin MSOP (AT24001A/02), 8-Pin TSSOP
(AT24C01A/02/04/08/16), and 8-Pin and 14-Pin JEDEC SOIC
(AT24C01A/02/04/08/16) packages and is accessed via a 2-wire serial interface. In
addition, the entire family is available in 5.0V (4.5V to 5.5V), 2.7V (2.7V to 5.5V), 2.5V
(2.5V to 5.5V) and 1.8V (1.8V to 5.5V) versions.
Pin Configurations
8-Pin TSSOP
Pin Name Function
A0 to A2 Address Inputs
SDA
Serial Data
SCL Serial Clock Input
WP Write Protect
NC No Connect
14-Pin SOIC
A0
A1
A2
GND
1
2
3
4
8 VCC
7 WP
6 SCL
5 SDA
8-Pin MSOP
A0
A1
A2
GND
1
2
3
4
8 VCC
7 WP
6 SCL
5 SDA
NC
A0
A1
NC
A2
GND
NC
1
2
3
4
5
6
7
14 NC
13 VCC
12 WP
11 NC
10 SCL
9 SDA
8 NC
8-Pin PDIP
A0
A1
A2
GND
1
2
3
4
8 VCC
7 WP
6 SCL
5 SDA
8-Pin SOIC
A0
A1
A2
GND
1
2
3
4
8 VCC
7 WP
6 SCL
5 SDA
2-Wire
Serial EEPROM
1K (128 x 8)
2K (256 x 8)
4K (512 x 8)
8K (1024 x 8)
16K (2048 x 8)
AT24C01A
AT24C02
AT24C04
AT24C08
AT24C16
2-Wire, 1K
Serial E2PROM
Rev. 0180D–06/98
1




AT24C16 pdf, 반도체, 판매, 대치품
AC Characteristics
Applicable over recommended operating range from TA = -40°C to +85°C, VCC = +1.8V to +5.5V, CL = 1 TTL Gate and
100pF (unless otherwise noted).
2.7-, 2.5-, 1.8-volt
5.0-volt
Symbol
Parameter
Min Max Min Max
Units
fSCL
tLOW
tHIGH
tI
tAA
tBUF
Clock Frequency, SCL
Clock Pulse Width Low
Clock Pulse Width High
Noise Suppression Time(1)
Clock Low to Data Out Valid
Time the bus must be free before
a new transmission can start(1)
100 400
4.7 1.2
4.0 0.6
100 50
0.1 4.5 0.1 0.9
4.7 1.2
kHz
µs
µs
ns
µs
µs
tHD.STA
Start Hold Time
tSU.STA
Start Set-up Time
tHD.DAT
Data In Hold Time
tSU.DAT
tR
tF
Data In Set-up Time
Inputs Rise Time(1)
Inputs Fall Time(1)
tSU.STO
Stop Set-up Time
tDH Data Out Hold Time
tWR
Endurance(1)
Write Cycle Time
5.0V, 25°C, Page Mode
Note: 1. This parameter is characterized and is not 100% tested.
4.0
4.7
0
200
4.7
100
1M
0.6 µs
0.6 µs
0 µs
100 ns
1.0 0.3 µs
300 300 ns
0.6 µs
50 ns
10 10 ms
1M Write Cycles
Device Operation
CLOCK and DATA TRANSITIONS: The SDA pin is nor-
mally pulled high with an external device. Data on the SDA
pin may change only during SCL low time periods (refer to
Data Validity timing diagram). Data changes during SCL
high periods will indicate a start or stop condition as
defined below.
START CONDITION: A high-to-low transition of SDA with
SCL high is a start condition which must precede any other
command (refer to Start and Stop Definition timing dia-
gram).
STOP CONDITION: A low-to-high transition of SDA with
SCL high is a stop condition. After a read sequence, the
stop command will place the EEPROM in a standby power
mode (refer to Start and Stop Definition timing diagram).
ACKNOWLEDGE: All addresses and data words are seri-
ally transmitted to and from the EEPROM in 8-bit words.
The EEPROM sends a zero to acknowledge that it has
received each word. This happens during the ninth clock
cycle.
STANDBY MODE: The AT24C01A/02/04/08/16 features a
low power standby mode which is enabled: (a) upon power-
up and (b) after the receipt of the STOP bit and the comple-
tion of any internal operations.
MEMORY RESET: After an interruption in protocol, power
loss or system reset, any 2-wire part can be reset by follow-
ing these steps:
1. Clock up to 9 cycles.
2. Look for SDA high in each cycle while SCL is high.
3. Create a start condition as SDA is high.
4 AT24C01A/02/04/08/16

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AT24C16 전자부품, 판매, 대치품
AT24C01A/02/04/08/16
Device Addressing
The 1K, 2K, 4K, 8K and 16K EEPROM devices all require
an 8-bit device address word following a start condition to
enable the chip for a read or write operation (refer to Figure
1).
The device address word consists of a mandatory one,
zero sequence for the first four most significant bits as
shown. This is common to all the EEPROM devices.
The next 3 bits are the A2, A1 and A0 device address bits
for the 1K/2K EEPROM. These 3 bits must compare to
their corresponding hard-wired input pins.
The 4K EEPROM only uses the A2 and A1 device address
bits with the third bit being a memory page address bit. The
two device address bits must compare to their correspond-
ing hard-wired input pins. The A0 pin is no connect.
The 8K EEPROM only uses the A2 device address bit with
the next 2 bits being for memory page addressing. The A2
bit must compare to its corresponding hard-wired input pin.
The A1 and A0 pins are no connect.
The 16K does not use any device address bits but instead
the 3 bits are used for memory page addressing. These
page addressing bits on the 4K, 8K, and 16K devices
should be considered the most significant bits of the data
word address which follows. The A0, A1 and A2 pins are no
connect.
The eighth bit of the device address is the read/write opera-
tion select bit. A read operation is initiated if this bit is high
and a write operation is initiated if this bit is low.
Upon a compare of the device address, the EEPROM will
output a zero. If a compare is not made, the chip will return
to a standby state.
Write Operations
BYTE WRITE: A write operation requires an 8-bit data
word address following the device address word and
acknowledgment. Upon receipt of this address, the
EEPROM will again respond with a zero and then clock in
the first 8-bit data word. Following receipt of the 8-bit data
word, the EEPROM will output a zero and the addressing
device, such as a microcontroller, must terminate the write
sequence with a stop condition. At this time the EEPROM
enters an internally-timed write cycle, tWR, to the nonvolatile
memory. All inputs are disabled during this write cycle and
the EEPROM will not respond until the write is complete
(refer to Figure 2).
PAGE WRITE: The 1K/2K EEPROM is capable of an 8-
byte page write, and the 4K, 8K and 16K devices are capa-
ble of 16-byte page writes.
A page write is initiated the same as a byte write, but the
microcontroller does not send a stop condition after the first
data word is clocked in. Instead, after the EEPROM
acknowledges receipt of the first data word, the microcon-
troller can transmit up to seven (1K/2K) or fifteen (4K, 8K,
16K) more data words. The EEPROM will respond with a
zero after each data word received. The microcontroller
must terminate the page write sequence with a stop condi-
tion (refer to Figure 3).
The data word address lower three (1K/2K) or four (4K, 8K,
16K) bits are internally incremented following the receipt of
each data word. The higher data word address bits are not
incremented, retaining the memory page row location.
When the word address, internally generated, reaches the
page boundary, the following byte is placed at the begin-
ning of the same page. If more than eight (1K/2K) or six-
teen (4K, 8K, 16K) data words are transmitted to the
EEPROM, the data word address will “roll over” and previ-
ous data will be overwritten.
ACKNOWLEDGE POLLING: Once the internally-timed
write cycle has started and the EEPROM inputs are dis-
abled, acknowledge polling can be initiated. This involves
sending a start condition followed by the device address
word. The read/write bit is representative of the operation
desired. Only if the internal write cycle has completed will
the EEPROM respond with a zero allowing the read or
write sequence to continue.
Read Operations
Read operations are initiated the same way as write opera-
tions with the exception that the read/write select bit in the
device address word is set to one. There are three read
operations: current address read, random address read
and sequential read.
CURRENT ADDRESS READ: The internal data word
address counter maintains the last address accessed dur-
ing the last read or write operation, incremented by one.
This address stays valid between operations as long as the
chip power is maintained. The address “roll over” during
read is from the last byte of the last memory page to the
first byte of the first page. The address “roll over” during
write is from the last byte of the current page to the first
byte of the same page.
Once the device address with the read/write select bit set
to one is clocked in and acknowledged by the EEPROM,
the current address data word is serially clocked out. The
microcontroller does not respond with an input zero but
does generate a following stop condition (refer to Figure 4).
RANDOM READ: A random read requires a “dummy” byte
write sequence to load in the data word address. Once the
device address word and data word address are clocked in
and acknowledged by the EEPROM, the microcontroller
must generate another start condition. The microcontroller
now initiates a current address read by sending a device
address with the read/write select bit high. The EEPROM
acknowledges the device address and serially clocks out
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