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PDF AT24C256 Data sheet ( Hoja de datos )
| Número de pieza | AT24C256 | |
| Descripción | 2-Wire Serial EEPROMs | |
| Fabricantes | ATMEL Corporation | |
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Features
• Low-voltage and Standard-voltage Operation
– 2.7 (VCC = 2.7V to 5.5V)
– 1.8 (VCC = 1.8V to 3.6V)
• Internally Organized 16,384 x 8 and 32,768 x 8
• Two-wire Serial Interface
• Schmitt Trigger, Filtered Inputs for Noise Suppression
• Bidirectional Data Transfer Protocol
• 1 MHz (5V), 400 kHz (2.7V, 2.5V) and 100 kHz (1.8V) Compatibility
• Write Protect Pin for Hardware and Software Data Protection
• 64-byte Page Write Mode (Partial Page Writes Allowed)
• Self-timed Write Cycle (5 ms Max)
• High Reliability
– Endurance: One Million Write Cycles
– Data Retention: 40 Years
• Extended Temperature and Lead-free/Halogen-free
Devices Available
• 8-lead JEDEC PDIP, 8-lead JEDEC and EIAJ SOIC, 8-lead MAP, 8-lead TSSOP, 8-lead
SAP and 8-ball dBGA2 Packages
• Die Sales: Wafer Form, Waffle Pack, and Bumped Wafers
Two-wire Serial
EEPROMs
128K (16,384 x 8)
256K (32,768 x 8)
Description
The AT24C128/256 provides 131,072/262,144 bits of serial electrically erasable and
programmable read only memory (EEPROM) organized as 16,384/32,768 words of 8
bits each. The device’s cascadable feature allows up to 4 devices to share a common
Two-wire bus. The device is optimized for use in many industrial and commercial appli-
cations where low power and low voltage operation are essential. The devices are
available in space-saving 8-lead JEDEC PDIP, 8-lead JEDEC SOIC, 8-lead EIAJ
SOIC, 8-lead MAP (24C128), 8-lead TSSOP, 8-lead SOIC Array Package and 8-ball
dBGA2 packages. In addition, the entire family is available in 2.7V (2.7V to 5.5V) and
1.8V (1.8V to 3.6V) versions.
Table 1. Pin Configuration
8-lead PDIP
8-lead TSSOP
Pin Name
A0 - A1
SDA
Function
Address Inputs
Serial Data
A0
A1
NC
GND
1
2
3
4
8 VCC
7 WP
6 SCL
5 SDA
A0
A1
NC
GND
1
2
3
4
8 VCC
7 WP
6 SCL
5 SDA
SCL
WP
NC
GND
Serial Clock Input
Write Protect
No Connect
Ground
8-lead SOIC
8-lead MAP
A0
A1
NC
GND
1
2
3
4
VCC 8
8 VCC WP 7
7 WP SCL 6
6 SCL SDA 5
5 SDA
1 A0
2 A1
3 NC
4 GND
8-ball dBGA2
VCC
WP
SCL
SDA
8
7
6
5
1 A0
2 A1
3 NC
4 GND
Bottom View
Bottom View
8-lead SAP
VCC 8
WP 7
SCL 6
SDA 5
1 A0
2 A1
3 NC
4 GND
Bottom View
AT24C128(1)
AT24C256(2)
Notes:
1. Not recommended for
new design; please
refer to AT24C128B
datasheet.
2. Not recommended for
new design; please
refer to AT24C256B
datasheet.
0670T–SEEPR–3/07
1
1 page  
AT24C128/256
Table 4. AC Characteristics – Industrial Temperatures
Applicable over recommended operating range from TAI = –40° C to +85° C, VCC = +1.8V to +5.5V, CL = 100 pF (unless oth-
erwise noted). Test conditions are listed in Note 2.
1.8-volt
2.5-volt
5.0-volt
Symbol
Parameter
Min Max Min Max Min Max Units
fSCL
tLOW
tHIGH
tAA
tBUF
Clock Frequency, SCL
Clock Pulse Width Low
Clock Pulse Width High
Clock Low to Data Out Valid
Time the bus must be free before a
new transmission can start(1)
4.7
4.0
0.1
4.7
100 400 1000
1.3 0.4
0.6 0.4
4.5 0.05 0.9 0.05 0.55
1.3 0.5
kHz
µs
µs
µs
µs
tHD.STA
tSU.STA
tHD.DAT
tSU.DAT
tR
tF
tSU.STO
tDH
tWR
Endurance(1)
Start Hold Time
Start Set-up Time
Data In Hold Time
Data In Set-up Time
Inputs Rise Time(1)
Inputs Fall Time(1)
Stop Set-up Time
Data Out Hold Time
Write Cycle Time
25°C, Page Mode
4.0 0.6 0.25
µs
4.7 0.6 0.25
µs
0 00
µs
200 100 100
ns
1.0 0.3 0.3 µs
300 300 100 ns
4.7 0.6 0.25
µs
100 50 50
ns
20 or 5(3)
10 or 5(3)
10 or 5(3)
ms
100k or 1,000,000(4)
Write
Cycles
Notes:
1. This parameter is characterized and is not 100% tested.
2. AC measurement conditions:
RL (connects to VCC): 1.3 kΩ (2.5V, 5V), 10 kΩ (1.8V)
Input pulse voltages: 0.3 VCC to 0.7 VCC
Input rise and fall times: ≤50 ns
Input and output timing reference voltages: 0.5 VCC
3. The Write Cycle Time of 5 ms only applies to the AT24C128/256 devices bearing the process letter “B” on the package (the
mark is located in the lower right corner on the top side of the package).
4. The AT24C128/256 bearing the process letter “B” in the package (the mark is located in the lower right corner on the top
side of the package), guarantees 1 million write cycle endurance (1.8 – 3.6V).
0670T–SEEPR–3/07
5
5 Page 
Read
Operations
AT24C128/256
Read operations are initiated the same way as write operations with the exception that the
read/write select bit in the device address word is set to one. There are three read operations:
current address read, random address read and sequential read.
CURRENT ADDRESS READ: The internal data word address counter maintains the last
address accessed during the last read or write operation, incremented by one. This address
stays valid between operations as long as the chip power is maintained. The address “roll
over” during read is from the last byte of the last memory page, to the first byte of the first
page.
Once the device address with the read/write select bit set to one is clocked in and acknowl-
edged by the EEPROM, the current address data word is serially clocked out. The
microcontroller does not respond with an input zero but does generate a following stop condi-
tion (see Figure 10 on page 12).
RANDOM READ: A random read requires a “dummy” byte write sequence to load in the data
word address. Once the device address word and data word address are clocked in and
acknowledged by the EEPROM, the microcontroller must generate another start condition.
The microcontroller now initiates a current address read by sending a device address with the
read/write select bit high. The EEPROM acknowledges the device address and serially clocks
out the data word. The microcontroller does not respond with a zero but does generate a fol-
lowing stop condition (see Figure 11 on page 12).
SEQUENTIAL READ: Sequential reads are initiated by either a current address read or a ran-
dom address read. After the microcontroller receives a data word, it responds with an
acknowledge. As long as the EEPROM receives an acknowledge, it will continue to increment
the data word address and serially clock out sequential data words. When the memory
address limit is reached, the data word address will “roll over” and the sequential read will con-
tinue. The sequential read operation is terminated when the microcontroller does not respond
with a zero but does generate a following stop condition (see Figure 12 on page 12).
Figure 7. Device Address
Figure 8. Byte Write
0670T–SEEPR–3/07
11
11 Page | ||
| Páginas | Total 23 Páginas | |
| PDF Descargar | [ Datasheet AT24C256.PDF ] | |
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