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PDF AT24C512 Data sheet ( Hoja de datos )
| Número de pieza | AT24C512 | |
| Descripción | 2-wire Serial EEPROM | |
| Fabricantes | ATMEL Corporation | |
| Logotipo |  |
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Features
• Low-voltage and Standard-voltage Operation
– 2.7 (VCC = 2.7V to 5.5V)
– 1.8 (VCC = 1.8V to 3.6V)
• Internally Organized 65,536 x 8
• Two-wire Serial Interface
• Schmitt Triggers, Filtered Inputs for Noise Suppression
• Bidirectional Data Transfer Protocol
• 1 MHz (5V), 400 kHz (2.7V) and 100 kHz (1.8V) Compatibility
• Write Protect Pin for Hardware and Software Data Protection
• 128-byte Page Write Mode (Partial Page Writes Allowed)
• Self-timed Write Cycle (5 ms Max)
• High Reliability
– Endurance: 100,000 Write Cycles
– Data Retention: 40 Years
• Automotive Devices Available
• 8-lead PDIP, 8-lead EIAJ SOIC, 8-lead JEDEC SOIC, 8-lead TSSOP,
8-lead LAP, 8-lead SAP and 8-ball dBGA2 Packages
• Die Sales: Wafer Form, Waffle Pack and Bumped Die
Description
The AT24C512 provides 524,288 bits of serial electrically erasable and programmable
read only memory (EEPROM) organized as 65,536 words of 8 bits each. The device’s
cascadable feature allows up to four devices to share a common two-wire bus. The
device is optimized for use in many industrial and commercial applications where low-
power and low-voltage operation are essential. The devices are available in space-
saving 8-pin PDIP, 8-lead EIAJ SOIC, 8-lead JEDEC SOIC, 8-lead TSSOP, 8-lead
Leadless Array (LAP), and 8-lead SAP packages. In addition, the entire family is avail-
able in 2.7V (2.7V to 5.5V) and 1.8V (1.8V to 3.6V) versions.
Table 1. Pin Configurations
Pin Name Function
A0–A1
Address Inputs
SDA
Serial Data
SCL Serial Clock Input
WP Write Protect
NC No Connect
8-lead TSSOP
8-lead PDIP
A0
A1
NC
GND
1
2
3
4
8 VCC
7 WP
6 SCL
5 SDA
A0
A1
NC
GND
1
2
3
4
8 VCC
7 WP
6 SCL
5 SDA
8-lead SOIC
A0
A1
NC
GND
1
2
3
4
8 VCC
7 WP
6 SCL
5 SDA
8-ball dBGA2
VCC
WP
SCL
SDA
8
7
6
5
1 A0
2 A1
3 NC
4 GND
Bottom View
8-lead Leadless Array
VCC 8
WP 7
SCL 6
SDA 5
1 A0
2 A1
3 NC
4 GND
Bottom View
8-lead SAP
VCC 8
WP 7
SCL 6
SDA 5
1 A0
2 A1
3 NC
4 GND
Bottom View
Two-wire Serial
EEPROM
512K (65,536 x 8)
AT24C512
Note: Not recommended for new
design; please refer to
AT24C512B datasheet.
Rev. 1116O–SEEPR–1/07
1
1 page  
AT24C512
Table 4. AC Characteristics
Applicable over recommended operating range from TA = –40°C to +85°C, VCC = +1.8V to +5.5V, CL = 100 pF (unless oth-
erwise noted) Test conditions are listed in Note 2.
1.8 Volt
2.7 Volt
5.0 Volt
Symbol
Parameter
Min Max Min Max Min Max
Units
fSCL
tLOW
tHIGH
tAA
tBUF
Clock Frequency, SCL
100 400 1000
Clock Pulse Width Low
4.7 1.3 0.4
Clock Pulse Width High
4.0 1.0 0.4
Clock Low to Data Out Valid
0.1 4.5 0.05 0.9 0.05 0.55
Time the bus must be free before a
new transmission can start(1)
4.7
1.3
0.5
kHz
µs
µs
µs
µs
tHD.STA
tSU.STA
tHD.DAT
tSU.DAT
tR
tF
tSU.STO
tDH
tWR
Endurance(1)
Start Hold Time
Start Set-up Time
Data In Hold Time
Data In Set-up Time
Inputs Rise Time(1)
Inputs Fall Time(1)
Stop Set-up Time
Data Out Hold Time
Write Cycle Time
5.0V, 25°C, Page Mode
4.0
4.7
0
200
4.7
100
100K
1.0
300
20 or 5(3)
0.6
0.6
0
100
0.6
50
100K
0.3
300
10 or 5(3)
0.25
0.25
0
100
0.25
50
100K
0.3
100
10 or 5(3)
µs
µs
µs
ns
µs
ns
µs
ns
ms
Write Cycles
Notes:
1. This parameter is characterized and is not 100% tested.
2. AC measurement conditions:
RL (connects to VCC): 1.3 kΩ (2.7V, 5V), 10 kΩ (1.8V)
Input pulse voltages: 0.3VCC to 0.7VCC
Input rise and fall times: ≤50 ns
Input and output timing reference voltages: 0.5VCC
3. The Write Cycle Time of 5 ms only applies to the AT24C512 devices bearing the process letter “A” on the package (the mark
is located in the lower right corner on the top side of the package).
1116O–SEEPR–1/07
5
5 Page 
Figure 8. Byte Write
Figure 9. Page Write
Figure 10. Current Address Read
Figure 11. Random Read
1116O–SEEPR–1/07
AT24C512
11
11 Page | ||
| Páginas | Total 22 Páginas | |
| PDF Descargar | [ Datasheet AT24C512.PDF ] | |
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