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AT24CS128 데이터시트 PDF




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부품번호 AT24CS128 기능
기능 2-Wire Serial EEPROMs
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AT24CS128 데이터시트, 핀배열, 회로
Features
One-time Programmable (OTP) Feature
Low-voltage and Standard-voltage Operation
– 5.0 (VCC = 4.5V to 5.5V)
– 2.7 (VCC = 2.7V to 5.5V)
– 1.8 (VCC = 1.8V to 3.6V)
Internally Organized 16,384 x 8 and 32,768 x 8
2-wire Serial Interface
Schmitt Trigger, Filtered Inputs for Noise Suppression
Bidirectional Data Transfer Protocol
1 MHz (5V), 400 kHz (2.7V) and 100 kHz (1.8V) Compatibility
Write Protect Pin for Hardware and Software Data Protection
64-byte Page Write Mode (Partial Page Writes Allowed)
Self-timed Write Cycle (5 ms typical)
High Reliability
– Endurance: 100,000 Write Cycles
– Data Retention: 40 Years
– ESD Protection: >4000V
Automotive Grade and Extended Temperature Devices Available
8-pin JEDEC PDIP and 8-pin JEDEC and EIAJ SOIC Packages
Description
The AT24CS128/256 provides 131,072/262,144 bits of serial electrically-erasable and
programmable read only memory (EEPROM) organized as 16,384/32,768 words of 8
bits each. The device’s cascadable feature allows up to 4 devices to share a common
2-wire bus. The device also features a one-time programmable 2048-bit array, which
once enabled, becomes read-only and cannot be overwritten. If not enabled, the OTP
section will function as part of the normal memory array. The device is optimized for
use in many industrial and commercial applications where low-power and low-voltage
operation are essential. The devices are available in space-saving 8-pin JEDEC PDIP
(AT24CS128/256), 8-pin EIAJ (AT24CS128/256), 8-pin JEDEC SOIC (AT24CS128)
packages. In addition, the entire family is available in 5.0V (4.5V to 5.5V), 2.7V (2.7V
to 5.5V) and 1.8V (1.8V to 3.6V) versions.
Pin Configurations
Pin Name
A0 - A2
SDA
SCL
WP
Function
Address Inputs
Serial Data
Serial Clock Input
Write Protect
PDIP
A0
A1
A2
GND
1
2
3
4
8 VCC
7 WP
6 SCL
5 SDA
Pin SOIC
2-wire Serial
EEPROMs
with Permanent
Software Write
Protect
128K (16,384 x 8)
256K (32,768 x 8)
AT24CS128
AT24CS256
A0
A1
A2
GND
1
2
3
4
8 VCC
7 WP
6 SCL
5 SDA
Rev. 1152B–05/01
1




AT24CS128 pdf, 반도체, 판매, 대치품
AC Characteristics
Applicable over recommended operating range from TA = -40°C to +85°C, VCC = +1.8V to +5.5V, CL = 100 pF (unless oth-
erwise noted). Test conditions are listed in Note 2.
1.8-volt
2.7-volt
5.0-volt
Symbol
Parameter
Min Max Min Max Min Max Units
fSCL
tLOW
tHIGH
tAA
tBUF
Clock Frequency, SCL
Clock Pulse Width Low
Clock Pulse Width High
Clock Low to Data Out Valid
Time the bus must be free before a new
transmission can start(1)
100 400 1000 kHz
4.7 1.3 0.6
µs
4.0 1.0 0.4
µs
0.1 4.5 0.05 0.9 0.05 0.55
µs
4.7 1.3 0.5
µs
tHD.STA
tSU.STA
tHD.DAT
tSU.DAT
tR
tF
tSU.STO
tDH
tWR
Endurance(1)
Start Hold Time
Start Set-up Time
Data In Hold Time
Data In Set-up Time
Inputs Rise Time(1)
Inputs Fall Time(1)
Stop Set-up Time
Data Out Hold Time
Write Cycle Time
5.0V, 25°C, Page Mode
Notes:
1. This parameter is characterized and is not 100% tested.
2. AC measurement conditions:
RL (connects to VCC): 1.3k(2.7V, 5V), 10k(1.8V)
Input pulse voltages: 0.3VCC to 0.7VCC
Input rise and fall times: 50ns
Input and output timing reference voltages: 0.5VCC
4.0 0.6 0.25
4.7 0.6 0.25
000
200 100 100
1.0 0.3 0.3
300 300 100
4.7 0.6 0.25
100 50
50
20 10 10
100K
100K
100K
µs
µs
µs
ns
µs
ns
µs
ns
ms
Write
Cycles
Device Operation
CLOCK and DATA TRANSITIONS: The SDA pin is nor-
mally pulled high with an external device. Data on the SDA
pin may change only during SCL low time periods (refer to
Data Validity timing diagram). Data changes during SCL
high periods will indicate a start or stop condition as defined
below.
START CONDITION: A high-to-low transition of SDA with
SCL high is a start condition which must precede any
other command (refer to Start and Stop Definition timing
diagram).
STOP CONDITION: A low-to-high transition of SDA with
SCL high is a stop condition. After a read sequence, the
stop command will place the EEPROM in a standby power
mode (refer to Start and Stop Definition timing diagram).
ACKNOWLEDGE: All addresses and data words are seri-
ally transmitted to and from the EEPROM in 8-bit words.
The EEPROM sends a zero during the ninth clock cycle to
acknowledge that it has received each word.
STANDBY MODE: The AT24CS128/256 features a low-
power standby mode which is enabled: a) upon power-up
and b) after the receipt of the STOP bit and the completion
of any internal operations.
MEMORY RESET: After an interruption in protocol, power
loss or system reset, any 2-wire part can be reset by follow-
ing these steps: (a) Clock up to 9 cycles, (b) look for SDA
high in each cycle while SCL is high and then (c) create a
start condition as SDA is high.
4 AT24CS128/256

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AT24CS128 전자부품, 판매, 대치품
AT24CS128/256
Device Addressing
The 128K/256K EEPROM requires an 8-bit device address
word following a start condition to enable the chip for a read
or write operation (refer to Figure 1). The device address
word consists of a mandatory one, zero sequence for the
first five most significant bits as shown. This is common to
all 2-wire EEPROM devices.
The 128K/256K uses the two device address bits A1, A0 to
allow as many as four devices on the same bus. These bits
must compare to their corresponding hardwired input pins.
The A1 and A0 pins use an internal proprietary circuit that
biases them to a logic low condition if the pins are allowed
to float.
The eighth bit of the device address is the read/write opera-
tion select bit. A read operation is initiated if this bit is high
and a write operation is initiated if this bit is low.
Upon a compare of the device address, the EEPROM will
output a zero. If a compare is not made, the device will
return to a standby state.
DATA SECURITY: The AT24CS128/256 has a hardware
data protection scheme that allows the user to write protect
the whole memory when the WP pin is at VCC.
Write Operations
BYTE WRITE: A write operation requires two 8-bit data
word addresses following the device address word and
acknowledgment. Upon receipt of this address, the
EEPROM will again respond with a zero and then clock in
the first 8-bit data word. Following receipt of the 8-bit data
word, the EEPROM will output a zero. The addressing
device, such as a microcontroller, then must terminate the
write sequence with a stop condition. At this time the
EEPROM enters an internally-timed write cycle, tWR, to the
nonvolatile memory. All inputs are disabled during this write
cycle and the EEPROM will not respond until the write is
complete (refer to Figure 2).
PAGE WRITE: The 128K/256K EEPROM is capable of 64-
byte page writes.
A page write is initiated the same way as a byte write, but
the microcontroller does not send a stop condition after the
first data word is clocked in. Instead, after the EEPROM
acknowledges receipt of the first data word, the microcon-
troller can transmit up to 63 more data words. The
EEPROM will respond with a zero after each data word
received. The microcontroller must terminate the page
write sequence with a stop condition (refer to Figure 3).
The data word address lower 6 bits are internally incre-
mented following the receipt of each data word. The higher
data word address bits are not incremented, retaining the
memory page row location. When the word address, inter-
nally generated, reaches the page boundary, the following
byte is placed at the beginning of the same page. If more
than 64 data words are transmitted to the EEPROM, the
data word address will roll overand previous data will be
overwritten. The address roll overduring write is from the
last byte of the current page to the first byte of the same
page.
ACKNOWLEDGE POLLING: Once the internally-timed
write cycle has started and the EEPROM inputs are dis-
abled, acknowledge polling can be initiated. This involves
sending a start condition followed by the device address
word. The read/write bit is representative of the operation
desired. Only if the internal write cycle has completed will
the EEPROM respond with a zero, allowing the read or
write sequence to continue.
OTP Description/Operation
The OTP feature provides the user with a 2048-bit (256 x 8)
security section, which once programmed and enabled,
becomes read-only and data cannot be changed or over-
written. The OTP section is located in the upper 2K section
of the memory array in the AT24CS128/256. If not enabled,
the OTP section will function as part of the normal memory
array.
To enable the OTP section:
1. Inputs must be connected:
A2 = Dont Care, A1 and A0 = VCC or GND
2. Initiate the programming sequence:
START 1010 1100 11xx xxxx xxxx xxxx xxxx xxxx STOP
Once enabled, previously written data cannot be changed.
The status of the OTP section can only be confirmed by ini-
tiating a programming sequence to the OTP section and
verifying by a read command. The use of the write protect
(WP) feature can be utilized with or without enabling the
OTP function.
Read Operations
Read operations are initiated the same way as write opera-
tions with the exception that the read/write select bit in the
device address word is set to one. There are three read
operations: current address read, random address read
and sequential read.
CURRENT ADDRESS READ: The internal data word
address counter maintains the last address accessed dur-
ing the last read or write operation, incremented by one.
This address stays valid between operations as long as the
chip power is maintained. The address roll overduring
read is from the last byte of the last memory page, to the
first byte of the first page.
Once the device address with the read/write select bit set
to one is clocked in and acknowledged by the EEPROM,
the current address data word is serially clocked out. The
microcontroller does not respond with an input zero but
does generate a following stop condition (refer to Figure 4).
7

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부품번호상세설명 및 기능제조사
AT24CS128

2-Wire Serial EEPROMs

ATMEL Corporation
ATMEL Corporation

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