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AT25020 데이터시트 PDF




ATMEL Corporation에서 제조한 전자 부품 AT25020은 전자 산업 및 응용 분야에서
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부품번호 AT25020 기능
기능 SPI Serial EEPROMs
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AT25020 데이터시트, 핀배열, 회로
Features
Serial Peripheral Interface (SPI) Compatible
Supports SPI Modes 0 (0,0) and 3 (1,1)
Low-voltage and Standard-voltage Operation
– 2.7 (VCC = 2.7V to 5.5V)
3.0 MHz Clock Rate (5V)
8-byte Page Mode
Block Write Protection
– Protect 1/4, 1/2, or Entire Array
Write Protect (WP) Pin and Write Disable Instructions for
Both Hardware and Software Data Protection
Self-timed Write Cycle (10 ms max)
High Reliability
– Endurance: One Million Write Cycles
– Data Retention: 100 Years
Automotive Grade Devices Available
8-lead PDIP and 8-lead JEDEC SOIC Packages
Description
The AT25010/020/040 provides 1024/2048/4096 bits of serial electrically erasable
programmable read only memory (EEPROM) organized as 128/256/512 words of 8
bits each. The device is optimized for use in many industrial and commercial applica-
tions where low-power and low voltage operation are essential. The AT25010/020/040
is available in space saving 8-lead PDIP and 8-lead JEDEC SOIC packages.
The AT25010/020/040 is enabled through the Chip Select pin (CS) and accessed via a
3-wire interface consisting of Serial Data Input (SI), Serial Data Output (SO), and
Serial Clock (SCK). All programming cycles are completely self-timed, and no sepa-
rate ERASE cycle is required before WRITE.
BLOCK WRITE protection is enabled by programming the status register with one of
four blocks of write protection. Separate program enable and program disable instruc-
tions are provided for additional data protection. Hardware data protection is provided
via the WP pin to protect against inadvertent write attempts. The HOLD pin may be
used to suspend any serial communication without resetting the serial sequence.
Pin Configurations
Pin Name
CS
SCK
Function
Chip Select
Serial Data Clock
SI
SO
GND
VCC
Serial Data Input
Serial Data Output
Ground
Power Supply
WP
HOLD
Write Protect
Suspends Serial Input
8-lead PDIP
CS
SO
WP
GND
1
2
3
4
8 VCC
7 HOLD
6 SCK
5 SI
8-lead SOIC
CS
SO
WP
GND
1
2
3
4
8 VCC
7 HOLD
6 SCK
5 SI
SPI Serial
EEPROMs
1K (128 x 8)
2K (256 x 8)
4K (512 x 8)
AT25010
AT25020
AT25040
Rev. 0606M–SEEPR–06/03
1




AT25020 pdf, 반도체, 판매, 대치품
AC Characteristics
Applicable over recommended operating range from TAI = -40°C to +85°C, VCC = As Specified, CL = 1 TTL Gate and
100 pF (unless otherwise noted).
Symbol
Parameter
Voltage
Min
Max Units
fSCK SCK Clock Frequency
4.5 - 5.5
2.7 - 5.5
0
0
3.0
2.1
MHz
tRI Input Rise Time
4.5 - 5.5
2.7 - 5.5
2
2
µs
tFI Input Fall Time
4.5 - 5.5
2.7 - 5.5
2
2
µs
tWH SCK High Time
4.5 - 5.5
2.7 - 5.5
133
200
ns
tWL SCK Low Time
4.5 - 5.5
2.7 - 5.5
133
200
ns
tCS CS High Time
4.5 - 5.5
2.7 - 5.5
250
250
ns
tCSS CS Setup Time
4.5 - 5.5
2.7 - 5.5
250
250
ns
tCSH CS Hold Time
4.5 - 5.5
2.7 - 5.5
250
250
ns
tSU Data In Setup Time
4.5 - 5.5
2.7 - 5.5
50
50
ns
tH Data In Hold Time
4.5 - 5.5
2.7 - 5.5
50
100
ns
tHD Hold Setup Time
4.5 - 5.5
2.7 - 5.5
100
100
ns
tCD Hold Hold Time
4.5 - 5.5
2.7 - 5.5
200
200
ns
tV Output Valid
4.5 - 5.5
2.7 - 5.5
0
0
133
200
ns
tHO Output Hold Time
4.5 - 5.5
2.7 - 5.5
0
0
ns
tLZ Hold to Output Low Z
4.5 - 5.5
2.7 - 5.5
0
0
100
100
ns
tHZ Hold to Output High Z
4.5 - 5.5
2.7 - 5.5
100
100
ns
tDIS Output Disable Time
4.5 - 5.5
2.7 - 5.5
250
500
ns
tWC Write Cycle Time
4.5 - 5.5
2.7 - 5.5
Endurance(1)
5.0V, 25°C, Page Mode
Note: 1. This parameter is characterized and is not 100% tested.
1M
5
10
ms
Write Cycles
4 AT25010/020/040
0606M–SEEPR–06/03

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AT25020 전자부품, 판매, 대치품
0606M–SEEPR–06/03
AT25010/020/040
WRITE ENABLE (WREN): The device will power up in the write disable state when VCC
is applied. All programming instructions must therefore be preceded by a Write Enable
instruction. The WP pin must be held high during a WREN instruction.
WRITE DISABLE (WRDI): To protect the device against inadvertent writes, the Write
Disable instruction disables all programming modes. The WRDI instruction is indepen-
dent of the status of the WP pin.
READ STATUS REGISTER (RDSR): The Read Status Register instruction provides
access to the status register. The READY/BUSY and Write Enable status of the device
can be determined by the RDSR instruction. Similarly, the Block Write Protection bits
indicate the extent of protection employed. These bits are set by using the WRSR
instruction.
Table 2. Status Register Format
Bit 7
Bit 6
Bit 5
Bit 4
XXXX
Bit 3
BP1
Bit 2
BP0
Bit 1
WEN
Bit 0
RDY
Table 3. Read Status Register Bit Definition
Bit Definition
Bit 0 (RDY)
Bit 0 = 0 (RDY) indicates the device is READY. Bit 0 = 1 indicates the
write cycle is in progress.
Bit 1 (WEN)
Bit 1 = 0 indicates the device is not WRITE ENABLED. Bit 1 = 1 indicates
the device is WRITE ENABLED.
Bit 2 (BP0)
See Table 4.
Bit 3 (BP1)
See Table 4.
Bits 4-7 are 0s when device is not in an internal write cycle.
Bits 0-7 are 1s during an internal write cycle.
WRITE STATUS REGISTER (WRSR): The WRSR instruction allows the user to select
one of four levels of protection. The AT25010/020/040 is divided into four array seg-
ments. Top quarter (1/4), Top half (1/2), or all of the memory segments can be
protected. Any of the data within any selected segment will therefore be READ only. The
block write protection levels and corresponding status register control bits are shown in
Table 4.
The two bits, BP1 and BP0 are nonvolatile cells that have the same properties and func-
tions as the regular memory cells (e.g. WREN, tWC, RDSR).
Table 4. Block Write Protect Bits
Level
Status Register Bits
BP1
BP0
Array Addresses Protected
AT25010
AT25020
AT25040
0
1 (1/4)
2 (1/2)
0
0
1
0
1
0
None
60-7F
40-7F
None
C0-FF
80-FF
None
180-1FF
100-1FF
3 (All)
1
1
00-7F
00-FF
000-1FF
7

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