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AT25020N-10SC-2.7 데이터시트 PDF




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기능 SPI Serial EEPROMs
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AT25020N-10SC-2.7 데이터시트, 핀배열, 회로
Features
Serial Peripheral Interface (SPI) Compatible
Supports SPI Modes 0(0,0) and 3(1,1)
Low-Voltage and Standard-Voltage Operation
– 5.0 (VCC = 4.5V to 5.5V)
– 2.7 (VCC = 2.7V to 5.5V)
– 1.8 (VCC = 1.8V to 3.6V)
2.1 MHz Clock Rate (5V) Compatibility
8-Byte Page Mode
Block Write Protection
– Protect 1/4, 1/2, or Entire Array
Write Protect (WP) Pin and Write Disable Instructions for
Both Hardware and Software Data Protection
Self-Timed Write Cycle (10 ms Max)
High Reliability
– Endurance: 1 Million Write Cycles
– Data Retention: 100 Years
– ESD Protection: >4000V
Automotive Grade and Extended Temperature Devices Available
8-Pin PDIP and JEDEC SOIC Packages
Description
The AT25010/020/040 provides 1024/2048/4096 bits of serial electrically erasable
programmable read only memory (EEPROM) organized as 128/256/512 words of 8
bits each. The device is optimized for use in many industrial and commercial applica-
tions where low power and low voltage operation are essential. The AT25010/020/040
is available in space saving 8-pin PDIP and 8-pin JEDEC (SOIC) packages.
The AT25010/020/040 is enabled through the Chip Select pin (CS) and accessed via
a 3-wire interface consisting of Serial Data Input (SI), Serial Data Output (SO), and
Serial Clock (SCK). All programming cycles are completely self-timed, and no sepa-
rate ERASE cycle is required before WRITE.
BLOCK WRITE protection is enabled by programming the status register with one of
four blocks of write protection. Separate program enable and program disable instruc-
tions are provided for additional data protection. Hardware data protection is provided
via the WP pin to protect against inadvertent write attempts. The HOLD pin may be
used to suspend any serial communication without resetting the serial sequence.
Pin Configurations
Pin Name
CS
SCK
SI
SO
GND
VCC
WP
HOLD
Function
Chip Select
Serial Data Clock
Serial Data Input
Serial Data Output
Ground
Power Supply
Write Protect
Suspends Serial Input
8-Pin PDIP
CS
SO
WP
GND
1
2
3
4
8 VCC
7 HOLD
6 SCK
5 SI
8-Pin SOIC
CS
SO
WP
GND
1
2
3
4
8 VCC
7 HOLD
6 SCK
5 SI
SPI Serial
EEPROMs
1K (128 x 8)
2K (256 x 8)
4K (512 x 8)
AT25010
AT25020
AT25040
SPI, 1K Serial
E2PROM
Rev. 0606E–08/98
1




AT25020N-10SC-2.7 pdf, 반도체, 판매, 대치품
AC Characteristics
Applicable over recommended operating range from TA = -40°C to +85°C, VCC = As Specified,
CL = 1 TTL Gate and 100 pF (unless otherwise noted).
Symbol
Parameter
Voltage
Min Max
fSCK SCK Clock Frequency
4.5 - 5.5 0 2.1
2.7 - 5.5 0 2.1
1.8 - 3.6 0 0.5
tRI Input Rise Time
4.5 - 5.5
2.7 - 5.5
1.8 - 3.6
2
2
2
tFI Input Fall Time
4.5 - 5.5
2.7 - 5.5
1.8 - 3.6
2
2
2
tWH SCK High Time
4.5 - 5.5
2.7 - 5.5
1.8 - 3.6
200
200
800
tWL SCK Low Time
4.5 - 5.5
2.7 - 5.5
1.8 - 3.6
200
200
800
tCS CS High Time
4.5 - 5.5
2.7 - 5.5
1.8 - 3.6
250
250
1000
tCSS CS Setup Time
4.5 - 5.5
2.7 - 5.5
1.8 - 3.6
250
250
1000
tCSH CS Hold Time
4.5 - 5.5
2.7 - 5.5
1.8 - 3.6
250
250
1000
tSU Data In Setup Time
4.5 - 5.5
2.7 - 5.5
1.8 - 3.6
50
50
100
tH Data In Hold Time
4.5 - 5.5
2.7 - 5.5
1.8 - 3.6
50
100
100
tHD Hold Setup Time
4.5 - 5.5
2.7 - 5.5
1.8 - 3.6
100
100
400
tCD Hold Hold Time
4.5 - 5.5
2.7 - 5.5
1.8 - 3.6
200
200
400
tV Output Valid
4.5 - 5.5
2.7 - 5.5
1.8 - 3.6
0 200
0 400
0 800
tHO Output Hold Time
4.5 - 5.5
2.7 - 5.5
1.8 - 3.6
0
0
0
4 AT25010/020/040
Units
MHz
µs
µs
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns

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AT25020N-10SC-2.7 전자부품, 판매, 대치품
AT25010/020/040
Functional Description
The AT25010/020/040 is designed to interface directly with
the synchronous serial peripheral interface (SPI) of the
6805 and 68HC11 series of microcontrollers.
The AT25010/020/040 utilizes an 8-bit instruction register.
The list of instructions and their operation codes are con-
tained in Table 1. All instructions, addresses, and data are
transferred with the MSB first and start with a high-to-low
CS transition.
Table 1. Instruction Set for the AT25010/020/040
Instruction Instruction
Name
Format
Operation
WREN
0000 X110 Set Write Enable Latch
WRDI
0000 X100 Reset Write Enable Latch
RDSR
0000 X101 Read Status Register
WRSR
0000 X001 Write Status Register
READ
0000 A011 Read Data from Memory Array
WRITE
0000 A010 Write Data to Memory Array
Note: “A” represents MSB address bit A8.
WRITE ENABLE (WREN): The device will power up in
the write disable state when VCC is applied. All program-
ming instructions must therefore be preceded by a Write
Enable instruction. The WP pin must be held high during a
WREN instruction.
WRITE DISABLE (WRDI): To protect the device against
inadvertent writes, the Write Disable instruction disables all
programming modes. The WRDI instruction is independent
of the status of the WP pin.
READ STATUS REGISTER (RDSR): The Read Status
Register instruction provides access to the status register.
The READY/BUSY and Write Enable status of the device
can be determined by the RDSR instruction. Similarly, the
Block Write Protection bits indicate the extent of protection
employed. These bits are set by using the WRSR instruc-
tion.
Table 2. Status Register Format
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3
X X X X BP1
Bit 2
BP0
Bit 1
WEN
Bit 0
RDY
Table 3. Read Status Register Bit Definition
Bit Definition
Bit 0 (RDY)
Bit 0 = 0 (RDY) indicates the device is
READY. Bit 0 = 1 indicates the write cycle
is in progress.
Bit 1 (WEN)
Bit 1 = 0 indicates the device is not WRITE
ENABLED. Bit 1 = 1 indicates the device is
WRITE ENABLED.
Bit 2 (BP0)
See Table 4.
Bit 3 (BP1)
See Table 4.
Bits 4-7 are 0s when device is not in an internal write cycle.
Bits 0-7 are 1s during an internal write cycle.
WRITE STATUS REGISTER (WRSR): The WRSR
instruction allows the user to select one of four levels of
protection. The AT25010/020/040 is divided into four array
segments. Top quarter (1/4), Top half (1/2), or all of the
memory segments can be protected. Any of the data within
any selected segment will therefore be READ only. The
block write protection levels and corresponding status reg-
ister control bits are shown in Table 4.
The two bits, BP1 and BP0 are nonvolatile cells that have
the same properties and functions as the regular memory
cells (e.g. WREN, tWC, RDSR).
Table 4. Block Write Protect Bits
Status
Register Bits
Array Addresses Protected
Level
BP1 BP0 AT25010 AT25020 AT25040
0 0 0 None None None
1 (1/4)
0
1
60-7F
C0-FF
180-1FF
2 (1/2)
1
0
40-7F
80-FF
100-1FF
3 (All)
1
1
00-7F
00-FF
000-1FF
READ SEQUENCE (READ): Reading the
AT25010/020/040 via the SO (Serial Output) pin requires
the following sequence. After the CS line is pulled low to
select a device, the READ op-code (including A8) is trans-
mitted via the SI line followed by the byte address to be
read (A7-A0). Upon completion, any data on the SI line will
be ignored. The data (D7-D0) at the specified address is
then shifted out onto the SO line. If only one byte is to be
read, the CS line should be driven high after the data
comes out. The READ sequence can be continued since
the byte address is automatically incremented and data will
continue to be shifted out. When the highest address is
reached, the address counter will roll over to the lowest
address allowing the entire memory to be read in one con-
tinuous READ cycle.
7

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AT25020N-10SC-2.7

SPI Serial EEPROMs

ATMEL Corporation
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