Datasheet.kr   

AT25256T2-10TC-1.8 데이터시트 PDF




ATMEL Corporation에서 제조한 전자 부품 AT25256T2-10TC-1.8은 전자 산업 및 응용 분야에서
광범위하게 사용되는 반도체 소자입니다.


PDF 형식의 AT25256T2-10TC-1.8 자료 제공

부품번호 AT25256T2-10TC-1.8 기능
기능 SPI Serial EEPROMs
제조업체 ATMEL Corporation
로고 ATMEL Corporation 로고


AT25256T2-10TC-1.8 데이터시트 를 다운로드하여 반도체의 전기적 특성과 매개변수에 대해 알아보세요.




전체 17 페이지수

미리보기를 사용할 수 없습니다

AT25256T2-10TC-1.8 데이터시트, 핀배열, 회로
Features
Serial Peripheral Interface (SPI) Compatible
Supports SPI Modes 0 (0,0) and 3 (1,1)
Low Voltage and Standard Voltage Operation
– 5.0 (VCC = 4.5V to 5.5V)
– 2.7 (VCC = 2.7V to 5.5V)
– 1.8 (VCC = 1.8V to 3.6V)
3 MHz Clock Rate
64-Byte Page Mode and Byte Write Operation
Block Write Protection
– Protect 1/4, 1/2, or Entire Array
Write Protect (WP) Pin and Write Disable Instructions for
Both Hardware and Software Data Protection
Self-Timed Write Cycle (5 ms Typical)
High Reliability
– Endurance: 100,000 Write Cycles
– Data Retention: >200 Years
– ESD Protection: >4000V
Automotive Grade and Extended Temperature Devices Available
8-Pin PDIP, 8-Pin EIAJ SOIC, 8-Pin and 16-Pin JEDEC SOIC, 14-Pin and 20-Pin TSSOP,
and 8-Pin Leadless Array Packages
Description
The AT25128/256 provides 131,072/262,144 bits of serial electrically erasable pro-
grammable read only memory (EEPROM) organized as 16,384/32,768 words of 8 bits
each. The device is optimized for use in many industrial and commercial applications
where low power and low voltage operation are essential. The devices are available in
Pin Configurations
(continued)
Pin Name Function
14-Lead TSSOP
CS
SCK
SI
SO
GND
VCC
WP
HOLD
NC
DC
Chip Select
Serial Data Clock
Serial Data Input
Serial Data Output
Ground
Power Supply
Write Protect
Suspends Serial Input
No Connect
Don't Connect
CS
SO
NC
NC
NC
WP
GND
1
2
3
4
5
6
7
14 VCC
13 HOLD
12 NC
11 NC
10 NC
9 SCK
8 SI
16-Pin SOIC
CS
SO
NC
NC
NC
NC
WP
GND
1
2
3
4
5
6
7
8
16 VCC
15 HOLD
14 NC
13 NC
12 NC
11 NC
10 SCK
9 SI
20-Lead TSSOP*
NC
CS
SO
SO
NC
NC
WP
GND
DC
NC
1
2
3
4
5
6
7
8
9
10
20 NC
19 VCC
18 HOLD
17 HOLD
16 NC
15 NC
14 SCK
13 SI
12 DC
11 NC
SPI Serial
EEPROMs
128K (16,384 x 8)
256K (32,768 x 8)
AT25128
AT25256
8-Pin PDIP
8-Pin SOIC
8-Pin Leadless Array
CS
SO
WP
GND
1
2
3
4
8 VCC
7 HOLD
6 SCK
5 SI
CS
SO
WP
GND
1
2
3
4
8 VCC
7 HOLD
6 SCK
5 SI
VCC 8
HOLD 7
SCK 6
SI 5
1 CS
2 SO
3 WP
4 GND
Bottom View
*Note: Pins 3, 4 and 17, 18 are internally connected for 14-lead TSSOP socket compatibility.
Rev. 0872E–08/98
1




AT25256T2-10TC-1.8 pdf, 반도체, 판매, 대치품
AC Characteristics
Applicable over recommended operating range from TA = -40°C to + 85°C, VCC = As Specified,
CL = 1 TTL Gate and 100 pF (unless otherwise noted).
Symbol
Parameter
Voltage
Min Max Units
fSCK SCK Clock Frequency
4.5 - 5.5
2.7 - 5.5
1.8 - 3.6
0 3.0
0 2.1 MHz
0 0.5
tRI Input Rise Time
4.5 - 5.5
2.7 - 5.5
1.8 - 3.6
2
2 µs
2
tFI Input Fall Time
4.5 - 5.5
2.7 - 5.5
1.8 - 3.6
2
2 µs
2
tWH SCK High Time
4.5 - 5.5
2.7 - 5.5
1.8 - 3.6
150
200 ns
800
tWL SCK Low Time
4.5 - 5.5
2.7 - 5.5
1.8 - 3.6
150
200 ns
800
tCS CS High Time
4.5 - 5.5
2.7 - 5.5
1.8 - 3.6
250
250
1000
ns
tCSS CS Setup Time
4.5 - 5.5
2.7 - 5.5
1.8 - 3.6
100
250
1000
ns
tCSH CS Hold Time
4.5 - 5.5
2.7 - 5.5
1.8 - 3.6
150
250
1000
ns
tSU Data In Setup Time
4.5 - 5.5
2.7 - 5.5
1.8 - 3.6
30
50 ns
100
tH Data In Hold Time
4.5 - 5.5
2.7 - 5.5
1.8 - 3.6
50
50 ns
100
tHD Hold Setup Time
4.5 - 5.5
2.7 - 5.5
1.8 - 3.6
100
100 ns
400
tCD Hold Hold Time
4.5 - 5.5
2.7 - 5.5
1.8 - 3.6
200
300 ns
400
tV Output Valid
4.5 - 5.5
2.7 - 5.5
1.8 - 3.6
0 150
0 200 ns
0 800
tHO Output Hold Time
4.5 - 5.5
2.7 - 5.5
1.8 - 3.6
0
0 ns
0
4 AT25128/256

4페이지










AT25256T2-10TC-1.8 전자부품, 판매, 대치품
AT25128/256
Functional Description
The AT25128/256 is designed to interface directly with the
synchronous serial peripheral interface (SPI) of the 6800
type series of microcontrollers.
The AT25128/256 utilizes an 8-bit instruction register. The
list of instructions and their operation codes are contained
in Table 1. All instructions, addresses, and data are trans-
ferred with the MSB first and start with a high-to-low CS
transition..
Table 1. Instruction Set for the AT25128/256
Instruction Instruction
Name
Format
Operation
WREN
0000 X110 Set Write Enable Latch
WRDI
0000 X100 Reset Write Enable Latch
RDSR
0000 X101 Read Status Register
WRSR
0000 X001 Write Status Register
READ
0000 X011 Read Data from Memory Array
WRITE
0000 X010 Write Data to Memory Array
WRITE ENABLE (WREN): The device will power up in the
write disable state when VCC is applied. All programming
instructions must therefore be preceded by a Write Enable
instruction.
WRITE DISABLE (WRDI): To protect the device against
inadvertent writes, the Write Disable instruction disables all
programming modes. The WRDI instruction is independent
of the status of the WP pin.
READ STATUS REGISTER (RDSR): The Read Status
Register instruction provides access to the status register.
The READY/BUSY and Write Enable status of the device
can be determined by the RDSR instruction. Similarly, the
Block Write Protection bits indicate the extent of protection
employed. These bits are set by using the WRSR instruc-
tion.
Table 2. Status Register Format
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
WPEN X X X BP1 BP0 WEN RDY
Table 3. Read Status Register Bit Definition
Bit Definition
Bit 0 (RDY) Bit 0 = 0 (RDY) indicates the device is READY.
Bit 0 = 1 indicates the write cycle is in progress.
Bit 1 (WEN)
Bit 1= 0 indicates the device is not WRITE
ENABLED. Bit 1 = 1 indicates the device is
WRITE ENABLED.
Bit 2 (BP0) See Table 4.
Bit 3 (BP1) See Table 4.
Bits 4-6 are 0s when device is not in an internal write cycle.
Bit 7
(WPEN)
See Table 5.
Bits 0-7 are 1s during an internal write cycle.
WRITE STATUS REGISTER (WRSR): The WRSR instruc-
tion allows the user to select one of four levels of protec-
tion. The AT25128/256 is divided into four array segments.
Top quarter (1/4), top half (1/2), or all of the memory seg-
ments can be protected. Any of the data within any
selected segment will therefore be READ only. The block
write protection levels and corresponding status register
control bits are shown in Table 4.
The three bits, BP0, BP1, and WPEN are nonvolatile cells
that have the same properties and functions as the regular
memory cells (e.g. WREN, tWC, RDSR).
Table 4. Block Write Protect Bits
Status Register Bits
Array Addresses
Protected
Level
BP1
BP0
AT25128
AT25256
0
0
0
None
None
1(1/4)
0
1 3000 - 3FFF 6000 - 7FFF
2(1/2)
1
0 2000 - 3FFF 4000 - 7FFF
3(All)
1
1 0000 - 3FFF 0000 - 7FFF
The WRSR instruction also allows the user to enable or
disable the write protect (WP) pin through the use of the
Write Protect Enable (WPEN) bit. Hardware write protec-
tion is enabled when the WP pin is low and the WPEN bit is
“1”. Hardware write protection is disabled when either the
WP pin is high or the WPEN bit is “0.” When the device is
hardware write protected, writes to the Status Register,
including the Block Protect bits and the WPEN bit, and the
block-protected sections in the memory array are disabled.
7

7페이지


구       성 총 17 페이지수
다운로드[ AT25256T2-10TC-1.8.PDF 데이터시트 ]

당사 플랫폼은 키워드, 제품 이름 또는 부품 번호를 사용하여 검색할 수 있는

포괄적인 데이터시트를 제공합니다.


구매 문의
일반 IC 문의 : 샘플 및 소량 구매
-----------------------------------------------------------------------

IGBT, TR 모듈, SCR 및 다이오드 모듈을 포함한
광범위한 전력 반도체를 판매합니다.

전력 반도체 전문업체

상호 : 아이지 인터내셔날

사이트 방문 :     [ 홈페이지 ]     [ 블로그 1 ]     [ 블로그 2 ]



관련 데이터시트

부품번호상세설명 및 기능제조사
AT25256T2-10TC-1.8

SPI Serial EEPROMs

ATMEL Corporation
ATMEL Corporation

DataSheet.kr       |      2020   |     연락처      |     링크모음      |      검색     |      사이트맵