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AT25F512N-10SI-2.7 데이터시트 PDF




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부품번호 AT25F512N-10SI-2.7 기능
기능 SPI Serial Memory
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AT25F512N-10SI-2.7 데이터시트, 핀배열, 회로
Features
Serial Peripheral Interface (SPI) Compatible
Supports SPI Modes 0 (0,0) and 3 (1,1)
20 MHz Clock Rate
Byte Mode and 256-byte Page Mode for Program Operations
Sector Architecture:
– Two Sectors with 32K Bytes Each (512K)
– Four Sectors with 32K Bytes Each (1M)
– 128 Pages per Sector
Product Identification Mode
Low-voltage Operation
– 2.7 (VCC = 2.7V to 3.6V)
Sector Write Protection
Write Protect (WP) Pin and Write Disable Instructions for
both Hardware and Software Data Protection
Self-timed Program Cycle (60 µs/Byte Typical)
Self-timed Sector Erase Cycle (1 second/Sector Typical)
Single Cycle Reprogramming (Erase and Program) for Status Register
High Reliability
– Endurance: 10,000 Write Cycles Typical
8-lead JEDEC SOIC
Description
The AT25F512/1024 provides 524,288/1,048,576 bits of serial reprogrammable Flash
memory organized as 65,536/131,072 words of 8 bits each. The device is optimized
for use in many industrial and commercial applications where low-power and low-volt-
age operation are essential. The AT25F512/1024 is available in a space-saving 8-lead
JEDEC SOIC package.
The AT25F512/1024 is enabled through the Chip Select pin (CS) and accessed via a
3-wire interface consisting of Serial Data Input (SI), Serial Data Output (SO), and
Serial Clock (SCK). All write cycles are completely self-timed.
BLOCK WRITE protection for top 1/4, top 1/2 or the entire memory array (1M) or
entire memory array (512K) is enabled by programming the status register. Separate
write enable and write disable instructions are provided for additional data protection.
Hardware data protection is provided via the WP pin to protect against inadvertent
write attempts to the status register. The HOLD pin may be used to suspend any serial
communication without resetting the serial sequence.
Pin Configurations
Pin Name
CS
SCK
Function
Chip Select
Serial Data Clock
SI
SO
GND
VCC
Serial Data Input
Serial Data Output
Ground
Power Supply
WP
HOLD
Write Protect
Suspends Serial Input
8-lead SOIC
CS
SO
WP
GND
1
2
3
4
8 VCC
7 HOLD
6 SCK
5 SI
SPI Serial
Memory
512K (65,536 x 8)
1M (131,072 x 8)
AT25F512
AT25F1024
Rev. 1440M–SEEPR–7/03
1




AT25F512N-10SI-2.7 pdf, 반도체, 판매, 대치품
AC Characteristics
Applicable over recommended operating range from TAI = -40°C to +85°C, VCC = +2.7V to +3.6V
CL = 1 TTL Gate and 30 pF (unless otherwise noted).
Symbol
Parameter
Min Typ Max
fSCK SCK Clock Frequency
0
tRI Input Rise Time
tFI Input Fall Time
tWH SCK High Time
20
tWL SCK Low Time
20
tCS CS High Time
25
tCSS CS Setup Time
25
tCSH CS Hold Time
25
tSU Data In Setup Time
5
tH Data In Hold Time
5
tHD Hold Setup Time
15
tCD Hold Time
15
tV Output Valid
tHO Output Hold Time
0
tLZ Hold to Output Low Z
tHZ Hold to Output High Z
tDIS Output Disable Time
tEC
tBPC
Endurance(2)
Erase Cycle Time per Sector
Byte Program Cycle Time(1)
60
10K
Notes: 1. The programming time for n bytes will be equal to n x tBPC.
2. This parameter is characterized at 3.0V, 25°C and is not 100% tested.
3. One write cycle consists of erasing a sector, followed by programming the same sector.
20
20
20
20
200
200
100
1.1
100
Units
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
s
µs
Write Cycles(3)
4 AT25F512/1024
1440M–SEEPR–7/03

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AT25F512N-10SI-2.7 전자부품, 판매, 대치품
Functional
Description
AT25F512/1024
The AT25F512/1024 is designed to interface directly with the synchronous serial periph-
eral interface (SPI) of the 6800 type series of microcontrollers.
The AT25F512/1024 utilizes an 8-bit instruction register. The list of instructions and their
operation codes are contained in Table 1. All instructions, addresses, and data are
transferred with the MSB first and start with a high-to-low transition.
Write is defined as program and/or erase in this specification. The following commands,
PROGRAM, SECTOR ERASE, CHIP ERASE, and WRSR are write instructions for
AT25F512/1024.
Table 1. Instruction Set for the AT25F512/1024
Instruction Name
Instruction
Format
Operation
WREN
0000 X110
Set Write Enable Latch
WRDI
0000 X100
Reset Write Enable Latch
RDSR
0000 X101
Read Status Register
WRSR
0000 X001
Write Status Register
READ
0000 X011
Read Data from Memory Array
PROGRAM
0000 X010
Program Data Into Memory Array
SECTOR ERASE
0101 X010
Erase One Sector in Memory Array
CHIP ERASE
0110 X010
Erase All Sectors in Memory Array
RDID
0001 X101
Read Manufacturer and Product ID
WRITE ENABLE (WREN): The device will power up in the write disable state when VCC
is applied. All write instructions must therefore be preceded by the WREN instruction.
WRITE DISABLE (WRDI): To protect the device against inadvertent writes, the WRDI
instruction disables all write commands. The WRDI instruction is independent of the sta-
tus of the WP pin.
READ STATUS REGISTER (RDSR): The RDSR instruction provides access to the sta-
tus register. The READY/BUSY and write enable status of the device can be determined
by the RDSR instruction. Similarly, the Block Write Protection bits indicate the extent of
protection employed. These bits are set by using the WRSR instruction. During internal
write cycles, all other commands will be ignored except the RDSR instruction.
Table 2. Status Register Format
Bit 7
Bit 6
Bit 5
WPEN
X
X
Bit 4
X
Bit 3
BP1
Bit 2
BP0
Bit 1
WEN
Bit 0
RDY
1440M–SEEPR–7/03
7

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부품번호상세설명 및 기능제조사
AT25F512N-10SI-2.7

SPI Serial Memory

ATMEL Corporation
ATMEL Corporation

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