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AT25HP256C1-10CC 데이터시트 PDF




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AT25HP256C1-10CC 데이터시트, 핀배열, 회로
Features
Serial Peripheral Interface (SPI) Compatible
Supports SPI Modes 0 (0,0) and 3 (1,1)
10 MHz Clock Rate
128-Byte Page Mode Only for Write Operations
Low-Voltage and Standard-Voltage Operation
– 5.0 (VCC = 4.5V to 5.5V)
– 2.7 (VCC = 2.7V to 5.5V)
– 1.8 (VCC = 1.8V to 3.6V)
Block Write Protection
– Protect 1/4, 1/2, or Entire Array
Write Protect (WP) Pin and Write Disable Instructions for
Both Hardware and Software Data Protection
High Reliability
– Endurance: 100K Write Cycles
– Data Retention: > 40 Years
– ESD Protection: > 3000V
8-Pin PDIP, 8-Pin EIAJ SOIC, and 8-Pin Leadless Array Package
Description
The AT25HP256/512 provides 262,144/524,288 bits of serial electrically erasable pro-
grammable read only memory (EEPROM) organized as 32,768/65,536 words of 8-bits
each. The device is optimized for use in many industrial and commercial applications
where high-speed, low-power, and low-voltage operation are essential. The
AT25HP256/512 is available in a space saving 8-pin PDIP (AT25HP256/512), 8-pin
EIAJ SOIC (AT25HP256), and 8-pin Leadless Array (AT25HP256/512) packages. In
(continued)
SPI Serial
EEPROMs
256K (32,768 x 8)
512K (65,536 x 8)
AT25HP256
AT25HP512
Preliminary
Pin Configurations
Pin Name
CS
SCK
SI
SO
GND
VCC
WP
HOLD
Function
Chip Select
Serial Data Clock
Serial Data Input
Serial Data Output
Ground
Power Supply
Write Protect
Suspends Serial Input
8-Pin PDIP
CS
SO
WP
GND
1
2
3
4
8 VCC
7 HOLD
6 SCK
5 SI
8-Pin SOIC
CS
SO
WP
GND
1
2
3
4
8 VCC
7 HOLD
6 SCK
5 SI
8-Pin Leadless Array
VCC 8
HOLD 7
SCK 6
SI 5
1 CS
2 SO
3 WP
4 GND
Bottom View
Rev. 1113B–07/98
1




AT25HP256C1-10CC pdf, 반도체, 판매, 대치품
AC Characteristics
Applicable over recommended operating range from TA = -40°C to +85°C, VCC = As Specified,
CL = 1 TTL Gate and 30 pF (unless otherwise noted).
Symbol
Parameter
Voltage
Min
fSCK SCK Clock Frequency
4.5 - 5.5
2.7 - 5.5
1.8 - 3.6
0
0
0
tRI Input Rise Time
4.5 - 5.5
2.7 - 5.5
1.8 - 3.6
tFI Input Fall Time
4.5 - 5.5
2.7 - 5.5
1.8 - 3.6
tWH SCK High Time
4.5 - 5.5
2.7 - 5.5
1.8 - 3.6
40
80
TBD
tWL SCK Low Time
4.5 - 5.5
2.7 - 5.5
1.8 - 3.6
40
80
TBD
tCS CS High Time
4.5 - 5.5
2.7 - 5.5
1.8 - 3.6
50
100
TBD
tCSS CS Setup Time
4.5 - 5.5
2.7 - 5.5
1.8 - 3.6
50
100
TBD
tCSH CS Hold Time
4.5 - 5.5
2.7 - 5.5
1.8 - 3.6
50
100
TBD
tSU Data In Setup Time
4.5 - 5.5
2.7 - 5.5
1.8 - 3.6
12
20
TBD
tH Data In Hold Time
4.5 - 5.5
2.7 - 5.5
1.8 - 3.6
10
20
TBD
tHD Hold Setup Time
4.5 - 5.5
2.7 - 5.5
1.8 - 3.6
25
50
TBD
tCD Hold Hold Time
4.5 - 5.5
2.7 - 5.5
1.8 - 3.6
25
50
TBD
tV Output Valid
4.5 - 5.5
2.7 - 5.5
1.8 - 3.6
0
0
0
tHO Output Hold Time
4.5 - 5.5
2.7 - 5.5
1.8 - 3.6
0
0
0
Max
10
5
TBD
2
2
TBD
2
2
TBD
40
80
TBD
Units
MHz
µs
µs
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
4 AT25HP256/512

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AT25HP256C1-10CC 전자부품, 판매, 대치품
AT25HP256/512
Functional Description
The AT25HP256/512 is designed to interface directly with
the synchronous serial peripheral interface (SPI) of the
6800 type series of microcontrollers.
The AT25HP256/512 utilizes an 8-bit instruction register.
The list of instructions and their operation codes are con-
tained in Table 1. All instructions, addresses, and data are
transferred with the MSB first and start with a high-to-low
CS transition.
Table 1. Instruction Set for the AT25HP256/512
Instruction Instruction
Name
Format
Operation
WREN
0000 X110 Set Write Enable Latch
WRDI
0000 X100 Reset Write Enable Latch
RDSR
0000 X101 Read Status Register
WRSR
0000 X001 Write Status Register
READ
0000 X011 Read Data from Memory Array
WRITE
0000 X010 Write Data to Memory Array
WRITE ENABLE (WREN): The device will power up in the
write disable state when VCC is applied. All programming
instructions must therefore be preceded by a Write Enable
instruction.
WRITE DISABLE (WRDI): To protect the device against
inadvertent writes, the Write Disable instruction disables all
programming modes. The WRDI instruction is independent
of the status of the WP pin.
READ STATUS REGISTER (RDSR): The Read Status
Register instruction provides access to the status register.
The READY/BUSY and Write Enable status of the device
can be determined by the RDSR instruction. Similarly, the
Block Write Protection bits indicate the extent of protection
employed. These bits are set by using the WRSR instruc-
tion.
Table 2. Status Register Format
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
WPEN X X X BP1 BP0 WEN RDY
Table 3. Read Status Register Bit Definition
Bit Definition
Bit 0 (RDY)
Bit 0 = 0 (RDY) indicates the device is
READY. Bit 0 = 1 indicates the write cycle is in
progress.
Bit 1 (WEN)
Bit 1= 0 indicates the device is not WRITE
ENABLED. Bit 1 = 1 indicates the device is
WRITE ENABLED.
Bit 2 (BP0)
See Table 4.
Bit 3 (BP1)
See Table 4.
Bits 4-6 are 0s when device is not in an internal write cycle.
Bit 7 (WPEN) See Table 5.
Bits 0-7 are 1s during an internal write cycle.
WRITE STATUS REGISTER (WRSR): The WRSR instruc-
tion allows the user to select one of four levels of protec-
tion. The AT25HP256/512 is divided into four array
segments. Top quarter (1/4), top half (1/2), or all of the
memory segments can be protected. Any of the data within
any selected segment will therefore be READ only. The
block write protection levels and corresponding status reg-
ister control bits are shown in Table 4.
The three bits, BP0, BP1, and WPEN are nonvolatile cells
that have the same properties and functions as the regular
memory cells (e.g. WREN, tWC, RDSR).
Table 4. Block Write Protect Bits
Status Register Bits Array Addresses Protected
Level BP1
BP0
AT25HP256/512
0 00
None
1(1/4)
0
1 6000 - 7FFF/C000 - FFFF
2(1/2)
1
0 4000 - 7FFF/8000 - FFFF
3(All)
1
1 0000 - 7FFF/0000 - FFFF
The WRSR instruction also allows the user to enable or
disable the write protect (WP) pin through the use of the
Write Protect Enable (WPEN) bit. Hardware write protec-
tion is enabled when the WP pin is low and the WPEN bit is
“1”. Hardware write protection is disabled when either the
WP pin is high or the WPEN bit is “0.” When the device is
hardware write protected, writes to the Status Register,
including the Block Protect bits and the WPEN bit, and the
block-protected sections in the memory array are disabled.
7

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