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AT25P1024C1-10CI-2.7 데이터시트 PDF




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AT25P1024C1-10CI-2.7 데이터시트, 핀배열, 회로
Features
Serial Peripheral Interface (SPI) Compatible
Supports SPI Modes 0 (0,0) and 3 (1,1)
2.1 MHz Clock Rate
128-Byte Page Mode Only for Write Operations
Low Voltage and Standard Voltage Operation
– 5.0 (VCC = 4.5V to 5.5V)
– 2.7 (VCC = 2.7V to 5.5V)
– 1.8 (VCC = 1.8V to 3.6V)
Block Write Protection
– Protect 1/4, 1/2, or Entire Array
Write Protect (WP) Pin and Write Disable Instructions for
Both Hardware and Software Data Protection
Self-Timed Write Cycle (5 ms Typical)
High Reliability
– Endurance: 100,000 Write Cycles
– Data Retention: >40 Years
– ESD Protection: >3000V
20-Pin JEDEC SOIC and 8-Pin Leadless Array Package
Description
The AT25P1024 provides 1,048,576 bits of serial electrically erasable programmable
read only memory (EEPROM) organized as 131,072 words of 8 bits each. The device
is optimized for use in many industrial and commercial applications where low power
and low voltage operation are essential. The AT25P1024 is available in space saving
20-pin JEDEC SOIC and 8-pin leadless array (LAP) packages.
Pin Configurations
(continued)
Pin Name
CS
SCK
SI
SO
GND
VCC
WP
HOLD
NC
Function
Chip Select
Serial Data Clock
Serial Data Input
Serial Data Output
Ground
Power Supply
Write Protect
Suspends Serial Input
No Connect
20-Lead SOIC
CS
SO
NC
NC
NC
NC
NC
NC
WP
GND
1
2
3
4
5
6
7
8
9
10
20 VCC
19 HOLD
18 NC
17 NC
16 NC
15 NC
14 NC
13 NC
12 SCK
11 SI
8-Pin LAP
VCC 8
HOLD 7
SCK 6
SI 5
1 CS
2 SO
3 WP
4 GND
Bottom View
SPI Serial
EEPROMs
1M (131,072 x 8)
AT25P1024
Preliminary
Rev. 1082C–08/98
1




AT25P1024C1-10CI-2.7 pdf, 반도체, 판매, 대치품
AC Characteristics
Applicable over recommended operating range from TA = -40°C to +85°C, VCC = As Specified,
CL = 1 TTL Gate and 100 pF (unless otherwise noted).
Symbol
Parameter
Voltage
Min
Max Units
fSCK SCK Clock Frequency
4.5 - 5.5
2.7 - 5.5
1.8 - 3.6
0 2.1
0 1.0 MHz
0 0.5
tRI Input Rise Time
4.5 - 5.5
2.7 - 5.5
1.8 - 3.6
2
2 µs
2
tFI Input Fall Time
4.5 - 5.5
2.7 - 5.5
1.8 - 3.6
2
2 µs
2
tWH SCK High Time
4.5 - 5.5
2.7 - 5.5
1.8 - 3.6
200
400 ns
800
tWL SCK Low Time
4.5 - 5.5
2.7 - 5.5
1.8 - 3.6
200
400 ns
800
tCS CS High Time
4.5 - 5.5
2.7 - 5.5
1.8 - 3.6
250
500
1000
ns
tCSS CS Setup Time
4.5 - 5.5
2.7 - 5.5
1.8 - 3.6
100
250
1000
ns
tCSH CS Hold Time
4.5 - 5.5
2.7 - 5.5
1.8 - 3.6
150
250
1000
ns
tSU Data In Setup Time
4.5 - 5.5
2.7 - 5.5
1.8 - 3.6
30
50 ns
100
tH Data In Hold Time
4.5 - 5.5
2.7 - 5.5
1.8 - 3.6
50
50 ns
100
tHD Hold Setup Time
4.5 - 5.5
2.7 - 5.5
1.8 - 3.6
100
100 ns
400
tCD Hold Hold Time
4.5 - 5.5
2.7 - 5.5
1.8 - 3.6
200
300 ns
400
tV Output Valid
4.5 - 5.5
2.7 - 5.5
1.8 - 3.6
0 200
0 400 ns
0 800
tHO Output Hold Time
4.5 - 5.5
2.7 - 5.5
1.8 - 3.6
0
0 ns
0
4 AT25P1024

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AT25P1024C1-10CI-2.7 전자부품, 판매, 대치품
AT25P1024
Functional Description
The AT25P1024 is designed to interface directly with the
synchronous serial peripheral interface (SPI) of the 6800
type series of microcontrollers.
The AT25P1024 utilizes an 8-bit instruction register. The
list of instructions and their operation codes are contained
in Table 1. All instructions, addresses, and data are trans-
ferred with the MSB first and start with a high-to-low transi-
tion.
Table 1. Instruction Set for the AT25P1024
Instruction Instruction
Name
Format
Operation
WREN
0000 X110 Set Write Enable Latch
WRDI
0000 X100 Reset Write Enable Latch
RDSR
0000 X101 Read Status Register
WRSR
0000 X001 Write Status Register
READ
0000 X011 Read Data from Memory Array
WRITE
0000 X010 Write Data to Memory Array
WRITE ENABLE (WREN): The device will power up in the
write disable state when VCC is applied. All programming
instructions must therefore be preceded by a Write Enable
instruction.
WRITE DISABLE (WRDI): To protect the device against
inadvertent writes, the Write Disable instruction disables all
programming modes. The WRDI instruction is independent
of the status of the WP pin.
READ STATUS REGISTER (RDSR): The Read Status
Register instruction provides access to the status register.
The READY/BUSY and Write Enable status of the device
can be determined by the RDSR instruction. Similarly, the
Block Write Protection bits indicate the extent of protection
employed. These bits are set by using the WRSR instruc-
tion.
Table 2. Status Register Format
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
WPEN X X X BP1 BP0 WEN RDY
Table 3. Read Status Register Bit Definition
Bit Definition
Bit 0 (RDY)
Bit 0 = 0 (RDY) indicates the device is
READY. Bit 0 = 1 indicates the write cycle is in
progress.
Bit 1 (WEN)
Bit 1= 0 indicates the device is not WRITE
ENABLED. Bit 1 = 1 indicates the device is
WRITE ENABLED.
Bit 2 (BP0)
See Table 4.
Bit 3 (BP1)
See Table 4.
Bits 4-6 are 0s when device is not in an internal write cycle.
Bit 7 (WPEN) See Table 5.
Bits 0-7 are 1s during an internal write cycle.
WRITE STATUS REGISTER (WRSR): The WRSR instruc-
tion allows the user to select one of four levels of protec-
tion. The AT25P1024 is divided into four array segments.
Top quarter (1/4), top half (1/2), or all of the memory seg-
ments can be protected. Any of the data within any
selected segment will therefore be READ only. The block
write protection levels and corresponding status register
control bits are shown in Table 4.
The three bits, BP0, BP1, and WPEN are nonvolatile cells
that have the same properties and functions as the regular
memory cells (e.g. WREN, tWC, RDSR).
Table 4. Block Write Protect Bits
Status Register Bits Array Addresses Protected
Level BP1
BP0
AT25P1024
0 00
None
1(1/4)
0
1
01800 - 01FFFF
2(1/2)
1
0
010000 - 01FFFF
3(All)
1
1
0000 - 01FFFF
The WRSR instruction also allows the user to enable or
disable the write protect (WP) pin through the use of the
Write Protect Enable (WPEN) bit. Hardware write protec-
tion is enabled when the WP pin is low and the WPEN bit is
“1”. Hardware write protection is disabled when either the
WP pin is high or the WPEN bit is “0.” When the device is
hardware write protected, writes to the Status Register,
including the Block Protect bits and the WPEN bit, and the
block-protected sections in the memory array are disabled.
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SPI Serial EEPROMs

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