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PDF AT27BV010-12TI Data sheet ( Hoja de datos )

Número de pieza AT27BV010-12TI
Descripción 1 Megabit 128K x 8 Unregulated Battery-Voltage OTP CMOS EPROM
Fabricantes ATMEL Corporation 
Logotipo ATMEL Corporation Logotipo



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AT27BV010
Features
Fast Read Access Time - 70 ns
•• Dual Voltage Range Operation
Unregulated Battery Power Supply Range, 2.7V to 3.6V
or Standard 5V ± 10% Supply Range
Compatible with JEDEC Standard AT27C010
•• Low Power CMOS Operation
20 µA max. (less than 1 µA typical) Standby for VCC = 3.6V
29 mW max. Active at 5 MHz for VCC = 3.6V
JEDEC Standard Packages
32-Lead PLCC
32-Lead TSOP
High Reliability CMOS Technology
2,000V ESD Protection
200 mA Latchup Immunity
RapidProgramming Algorithm - 100 µs/byte (typical)
CMOS and TTL Compatible Inputs and Outputs
JEDEC Standard for LVTTL and LVBO
Integrated Product Identification Code
•• Commercial and Industrial Temperature Ranges
Description
The AT27BV010 is a high performance, low power, low voltage 1,048,576 bit one-
time programmable read only memory (OTP EPROM) organized as 128K by 8 bits.
It requires only one supply in the range of 2.7V to 3.6V in normal read mode opera-
tion, making it ideal for fast, portable systems using either regulated or unregulated
battery power.
Atmel’s innovative design techniques provide fast speeds that rival 5V parts while
keeping the low power consumption of a 3V supply. At VCC = 2.7V, any byte can be
accessed in less than 70 ns. With a typical power draw of only 18 mW at 5 MHz and
VCC = 3V, the AT27BV010 consumes less than one fifth the power of a standard 5V
Pin Configurations
(continued)
Pin Name
A0 - A16
O0 - O7
CE
OE
PGM
NC
Function
Addresses
Outputs
Chip Enable
Output Enable
Program Strobe
No Connect
PLCC Top View
TSOP Top View
Type 1
1 Megabit
(128K x 8)
Unregulated
Battery-Voltage
OTP
CMOS EPROM
AT27BV010
0344E
3-23

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AT27BV010-12TI pdf
AT27BV010
AC Characteristics for Read Operation (VCC = 2.7V to 3.6V and 4.5V to 5.5V)
AT27BV010
-70 -90 -12 -15
Symbol
tACC (3)
tCE (2)
tOE (2, 3)
tDF (4, 5)
tOH
Parameter
Condition
Address to Output Delay
CE = OE = VIL
CE to Output Delay
OE = VIL
OE to Output Delay
CE = VIL
OE or CE High to Output Float, whichever occurred first
Output Hold from Address, CE or OE,
whichever occurred first
Min Max Min Max Min Max Min Max Units
70 90 120 150 ns
70 90 120 150 ns
50 50
50 60 ns
40 40
40 50 ns
0 0 0 0 ns
Notes: 2, 3, 4, 5. - see AC Waveforms for Read Operation.
= Preliminary Information
AC Waveforms for Read Operation (1)
Notes: 1. Timing measurement references are 0.8V and 2.0V.
Input AC drive levels are 0.45V and 2.4V, unless
otherwise specified.
2. OE may be delayed up to tCE - tOE after the falling
edge of CE without impact on tCE .
3. OE may be delayed up to tACC - tOE after the address
is valid without impact on tACC .
4. This parameter is only sampled and is not 100% tested.
5. Output float is defined as the point when data is no longer
driven.
3-27

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