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PDF ARM920T Data sheet ( Hoja de datos )

Número de pieza ARM920T
Descripción System-on-Chip Platform OS Processor
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®
Product Overview
ARM920T
System-on-Chip Platform OS Processor
Applications
• Applications running a
platform OS:
- EPOC
- Linux
- WindowsCE
• High performance wireless
applications:
- Smart phones
- PDAs
• Networking applications
• Digital set top boxes
• Imaging
• Automotive control
solutions
• Audio and video encoding
and decoding
Benefits
• Designed specifically for
System-On-Chip
integration
• Supports the Thumb
instruction set offering the
same excellent code
density as the ARM7TDMI.
• High performance allows
system designers to
integrate more functionality
into price and
power-sensitive
applications demanding
more performance
• Cached processor with an
easy to use lower
frequency on-chip system
bus interface.
The ARM920T™
The ARM920T is a a high-performance 32-bit RISC integer processor
macrocell combining an ARM9TDMI™ processor core with:
• 16KB instruction and 16KB data caches
• instruction and data Memory Management Units (MMUs)
• write buffer
• an AMBA™ (Advanced Microprocessor Bus Architecture) bus interface
• an Embedded Trace Macrocell (ETM) interface.
High performance
The ARM920T provides a high-performance processor solution for open
systems requiring full virtual memory management and sophisticated memory
protection. An enhanced ARM® architecture version 4 MMU implementation
provides translation and access permission checks for instruction and data
addresses.
The ARM920T high-performance processor solution gives considerable
savings in chip complexity and area, chip system design, and power
consumption.
Compatible with ARM7™ and StrongARM®
The ARM920T processor is 100% user code binary compatible with
ARM7TDMI and backwards compatible with the ARM7 Thumb® Family and
the StrongARM processor families, giving designers software-compatible
processors with a range of price/performance points from 60 MiPS to 200+
MIPS. Support for the ARM architecture today includes:
• WindowsCE, EPOC, Linux, and QNX operating systems
• 40+ Real Time Operating Systems
• cosimulation tools from leading EDA vendors
• variety of software development tools.
.
DVI 0024A
© Copyright ARM Limited 2000. All rights reserved.
ARM Confidential - Draft
Page 1

1 page




ARM920T pdf
The ARMv4T Architecture
Load and store single register
instructions can transfer a 32-bit
word, a 16-bit halfword and an 8-bit
byte between memory and a register.
Byte and halfword loads might be
automatically zero extended or sign
extended as they are loaded. Swap
instructions perform an atomic load
and store as a synchronization
primitive.
Addressing modes
Load and store instructions have
three primary addressing modes:
• offset
• pre-indexed
• post-indexed.
They are formed by adding or
subtracting an immediate or register-
based offset to or from a base
register. Register-based offsets can
also be scaled with shift operations.
Pre-indexed and post-indexed
addressing modes update the base
register with the base plus offset
calculation. As the PC is a general-
purpose register, a 32-bit value can
be loaded directly into the PC to
perform a jump to any address in the
4GB memory space.
Block transfers
Load and store multiple instructions
perform a block transfer of any
number of the general purpose
registers to or from memory. Four
addressing modes are provided:
• pre-increment addressing
• post-increment addressing
• pre-decrement addressing
• post-decrement addressing.
The base address is specified by a
register value (that can be optionally
updated after the transfer). As the
subroutine return address and the
PC values are in general-purpose
registers, very efficient subroutine
calls can be constructed.
Branch
As well as allowing any data
processing or load instruction to
change control flow (by writing the
PC) a standard branch instruction is
provided with 24-bit signed offset,
allowing forward and backward
branches of up to 32MB.
Branch with Link
There is a Branch with Link (BL) that
allows efficient subroutine calls. BL
preserves the address of the
instruction after the branch in R14
(the Link Register or LR). This allows
a move instruction to put the LR in to
the PC and return to the instruction
after the branch.
The third type of branch (BX and
BLX) switches between ARM and
Thumb instruction sets optionally
with the return address preserving
link option.
Coprocessor
There are three types of coprocessor
instructions:
• coprocessor data processing
instructions invoke a
coprocessor specific internal
operation
• coprocessor register transfer
instructions allow a coprocessor
value to be transferred to or from
an ARM register
• coprocessor data transfer
instructions transfer coprocessor
data to or from memory, where
the ARM calculates the address
of the transfer.
DVI 0024A
© Copyright ARM Limited 2000. All rights reserved.
ARM Confidential - Draft
Page 5

5 Page





ARM920T arduino
System Issues and Third Party Support
JTAG debug
The internal state of the ARM920T
is examined through a JTAG-style
serial interface, which allows
instructions to be serially inserted
into the pipeline of the core without
using the external data bus.
Therefore, when in debug state, a
store-multiple (STM) can be
inserted into the instruction pipeline.
This exports the contents of the
ARM9TDMI registers. This data can
be serially shifted out without
affecting the rest of the system.
AMBA bus architecture
The ARM9 Thumb Family
processors are designed for use
with the AMBA multi-master on-chip
bus architecture. AMBA includes an
Advanced System Bus (ASB)
connecting processors and high-
bandwidth peripherals and memory
interfaces, and a low-power
peripheral bus allowing a large
number of low-bandwidth
peripherals.
The ARM920T ASB implementation
provides a 32-bit address bus and a
32-bit data bus for high-bandwidth
data transfers made possible by on-
chip memory and modern SDRAM
and RAMBUS memories.
Everything you need
ARM provides a wide range of
products and services to support its
processor families, including
software development tools,
development boards, models,
applications software, training, and
consulting services.
The ARM Architecture today enjoys
broad third party support. The
ARM9 Thumb Family processors
strong software compatibility with
existing ARM families ensures that
its users benefit immediately from
existing support. ARM is working
with its software, EDA, and
semiconductor partners to extend
this support to use new ARM9
Family features.
Current support
Support for the ARM Architecture
today includes:
ARM Developer Suite (ADS)
- Integrated development
environment
- C, C++, assembler, simulators
and windowing source-level
debugger
- Available on Windows95,
WindowsNT, and Unix.
- ARM Multi-ICE™ JTAG
interface
- Allows EmbeddedICE
software debug of ARM
processor systems
- integrates with the ADS.
• ARMulator instruction-accurate
software simulator
• Development boards
• Design Simulation Models
provide signoff quality ASIC-
simulation
• Software toolkits available from
ARM, Cygnus/GNU,Greenhills,
JavaSoft, MetaWare, Microtec,
and Windriver allowing software
development in C, C++, Java,
FORTRAN, Pascal, Ada, and
assembler.
• 20+ Real Time Operating
Systems including:
- Windriver VxWorks
- Sun Microsystems Chorus
- JavaOS
- Microtec VRTX
- JMI
- Embedded System Products
RTXC
- Integrated Systems pSOS.
• Major OS including:
- Microsoft WindowsCE
- PSION EPOC
- NetBSD
- Linux UNIX
- Geoworks
• Application software
components:
- speech and image
compression
- software modem
- Chinese character input
network protocols
- Digital AC3 decode
- MPEG3 encode and decode
- MPEG4 decode and encode
• Hardware/software
cosimulation tools from leading
EDA Vendors.
For more information, see
www.arm.com
DVI 0024A
© Copyright ARM Limited 2000. All rights reserved.
ARM Confidential - Draft
Page 11

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